Results 31 to 40 of about 17,773 (197)
High Linearity SAR ADC for Smart Sensor Applications [PDF]
, 2018 This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor ...
Cen, Yuanjun +7 more
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Comparator Design in Sensors for Environmental Monitoring [PDF]
, 2018 This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate ...
Fan, Hua +4 more
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Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors [PDF]
, 2019 This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving.
Delgado Restituto, Manuel +2 more
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Low-Power SAR ADCs: Basic Techniques and Trends
IEEE Open Journal of the Solid-State Circuits Society, 2022 With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology ...
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Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update [PDF]
, 2016 This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and ...
Pickering, J.
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IEEE Access, 2021 This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to ...
Jae Sik Yoon +3 more
doaj +1 more source
A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s [PDF]
, 2010 This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and
Elzakker, Michiel van +5 more
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PixFEL: development of an X-ray diffraction imager for future FEL applications [PDF]
, 2017 A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm.
Battignani, Giovanni +21 more
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Free Speech and Its Relation to Self-Government by Alexander Meiklejohn [PDF]
, 1949 In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog ...
Fraenkel, Osmond K.
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Facta universitatis - series: Electronics and Energetics, 2020 The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels.
Dmitry Osipov +3 more
openaire +2 more sources