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Towards a cybersecure and privacy enhanced smart grid: A blockchain enabled federated learning framework. [PDF]
Tariq F +5 more
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MH-1M: A 1.34 Million-Sample Multi-Feature Android Malware Dataset with Rich Metadata. [PDF]
Bragança H +4 more
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AI-powered digital arbitration framework leveraging smart contracts and electronic evidence authentication. [PDF]
Han P.
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A Hybrid Multi-Scale Transformer-CNN UNet for Crowd Counting. [PDF]
Zhao K, He C, Peng S, Lu T.
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An image encryption scheme using PRESENT-RC4, chaos and secure key generation. [PDF]
Kumar K, Roy S, Puri D, Kumar R.
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A High-Throughput Hardware Implementation of SHA-256 Algorithm
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020The SHA-256 algorithm is widely used in the field of security. In this paper, we propose a rescheduling method for the SHA-256 round computation. Based on the proposed rescheduling, we propose a design for SHA-256, in which the critical path is reduced. Our design is implemented on the Xilinx Virtex-4 FPGA.
Yimeng Chen, Shuguo Li
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Multiple Hashing Using SHA-256 and MD5
2021Message Digest 5 (MD5) is a hashing function with numerous vulnerabilities such as pre-image vulnerability and collision vulnerability which restrict the usage of MD5. Therefore, by using other hashing functions such as SHA prior to hashing with MD5, we can use MD5 for various applications such as data integrity without compromising the security of the
Gautham P. Reddy +4 more
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Использование алгоритма SHA-256 для хеширования данных
ТЕНДЕНЦИИ РАЗВИТИЯ НАУКИ И ОБРАЗОВАНИЯ, 2022В современном мире как никогда важны криптографические хеш-функции, используемые для выполнения большого спектра задач, в которых важна защита данных. Алгоритмов хеширования в мире насчитывается огромное количество. Одним из наиболее распространенных и защищенных является алгоритм SHA-256.
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VLSI implementation of high-speed SHA-256
2009 IEEE 8th International Conference on ASIC, 2009To accelerate the speed of iterative computation for the existing SHA-256 algorithm, using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper. The frequency of the proposed scheme is 1.7 times higher than other VLSI implementations under the same process.
null Ling Bai, null Shuguo Li
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