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Soft errors: is the concern for soft-errors overblown?
IEEE International Conference on Test, 2005., 2006Cosmic ray particles have the ability to either toggle the state of memory elements or create unwanted glitches in combinational logic that may be latched by memory elements. As supply voltages reduce and feature sizes become smaller in future technologies, soft error tolerance is considered a significant challenge for designing future electronic ...
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Soft Error Mitigation in Soft-Core Processors
2016This chapter aims to present different approaches and techniques available in literature regarding the fault mitigation on soft-core processors, with an especial emphasis on those ones involving hardware/software hybrid-based solutions.
Antonio Martínez-Álvarez +2 more
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A soft error rate analysis (SERA) methodology
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004., 2005We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation.
M. Zhang, N.R. Shanbhag
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2018
We will begin by a quick but thorough look at the effects of faults, errors and failures, caused by terrestrial neutrons originating from cosmic rays, on the terrestrial electronic systems in the variety of industries. Mitigation measures, taken at various levels of design hierarchy from physical to systems level against neutron-induced adverse effects,
Eishi H. Ibe +13 more
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We will begin by a quick but thorough look at the effects of faults, errors and failures, caused by terrestrial neutrons originating from cosmic rays, on the terrestrial electronic systems in the variety of industries. Mitigation measures, taken at various levels of design hierarchy from physical to systems level against neutron-induced adverse effects,
Eishi H. Ibe +13 more
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SIMD-based soft error detection
Proceedings of the ACM International Conference on Computing Frontiers, 2016Soft error rates in processors have been increasing with decreasing feature size and larger chips. Software-only solutions have been proposed to deal with this problem, for instance via instruction duplication. However, this leads to significant overheads in performance and energy.
Zhi Chen +2 more
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2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
This paper presents a construction of a flip-flop (FF) that works as a soft error tolerant FF in system operations and as a BILBO (Built-In Logic Block Observer) FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft error tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF.
Kazuteru Namba, Hideo Ito
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This paper presents a construction of a flip-flop (FF) that works as a soft error tolerant FF in system operations and as a BILBO (Built-In Logic Block Observer) FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft error tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF.
Kazuteru Namba, Hideo Ito
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Software-Level Soft-Error Mitigation Techniques
2010Several application domains exist, where the effects of Soft Errors on processor-based systems cannot be faced by acting on the hardware (either by changing the technology, or the components, or the architecture, or whatever else). In these cases, an attractive solution lies in just modifying the software: the ability to detect and possibly correct ...
REBAUDENGO, Maurizio +2 more
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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 2003
Although the industry has long known about soft errors, customer awareness and concern about soft errors has recently increased. Advances in customer education, estimation techniques, and materials quality assist an ASIC designer in reducing soft-error system fails.
L. Wissel +4 more
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Although the industry has long known about soft errors, customer awareness and concern about soft errors has recently increased. Advances in customer education, estimation techniques, and materials quality assist an ASIC designer in reducing soft-error system fails.
L. Wissel +4 more
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Protecting Caches from Soft Errors
ACM Transactions on Embedded Computing Systems, 2017Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity ...
Yohan Ko +4 more
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Processor Design for Soft Errors
ACM Computing Surveys, 2016Today, soft errors are one of the major design technology challenges at and beyond the 22nm technology nodes. This article introduces the soft error problem from the perspective of processor design. This article also provides a survey of the existing soft error mitigation methods across different levels of design abstraction involved in processor ...
Tuo Li +3 more
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