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Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism [PDF]
Frontiers in Computational Neuroscience, 2023 Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this
Yu Xie +3 more
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Hybrid Lockstep Technique for Soft Error Mitigation
IEEE Transactions on Nuclear Science, 2022 This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer.
M. Pena-Fernandez +7 more
openaire +5 more sources
Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs
IEEE Access, 2020 Soft-core processors implemented in SRAM-based FPGAs are an attractive option for applications to be employed in radiation environments due to their flexibility, relatively-low application development costs, and reconfigurability features enabling them ...
Server Kasap +4 more
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A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories
Computers, 2017 Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey
Sparsh Mittal
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Machine learning based adaptive soft error mitigation efficiency
Machine Learning with ApplicationsThis work presents a novel adaptive framework for soft error mitigation in space-based systems, designed to resolve the fundamental conflict between system performance and radiation protection.
Nicholas Maurer, Mohammed Abdallah
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An Evolutionary Approach to the Soft Error Mitigation Technique for Cell-Based Design
Advances in Electrical and Computer Engineering, 2015 In this paper, we present a soft error mitigation algorithm that searches for the proper gate sizes within constrained gate-level designs. The individual gate sizing has an impact on the former optimization results and degrades the quality of the ...
PARK, J. K., KIM, J. T.
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Soft error mitigation techniques for future chip multiprocessors
, 2023 The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for next-generation designs. Following Moore's law, the exponential growth in the number of transistors per chip has brought tremendous ...
Gaurang Upasani
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Robust C-element design for soft-error mitigation
IEICE Electronics Express, 2015 C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device.
I-Chyn Wey +4 more
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Analysis of Kernel Redundancy for Soft Error Mitigation on Embedded GPUs
IEEE Transactions on Nuclear Science, 2023 The use of state-of-the-art commercial processors such as graphical processing units (GPUs) is becoming increasingly common in the New Space industry to ensure high performance and power efficiency. However, commercial GPUs are not designed to operate in
A. Serrano-Cases +4 more
semanticscholar +1 more source
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2021 Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to
Geancarlo Abich +4 more
semanticscholar +1 more source