Results 1 to 10 of about 139,876 (307)
Applying Reinforcement Learning to Protect Deep Neural Networks from Soft Errors [PDF]
With the advance of Artificial Intelligence, Deep Neural Networks are widely employed in various sensor-based systems to analyze operational conditions.
Peng Su +3 more
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Optimized Multiple-Bit-Flip Soft-Errors-Tolerant TCAM using Machine Learning
Soft errors from radiations can change the data in electronic devices especially memory cells such as in TCAMs. The soft errors cause bit-flip errors that makes the data are corrupted in the network.
Infall Syafalni, Trio Adiono
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SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical.
Waqas Gul +2 more
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Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell
Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems.
Bharathi Raj Muthu +6 more
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Space Electrostatic Discharge Effect (SESD) and Single Event Effect (SEE) are two major space environmental factors that cause spacecraft failure. Previous studies have established that both can lead to soft errors such as upset of memory cells.
Xuan Wang +5 more
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SEDAR: Soft Error Detection and Automatic Recovery in High Performance Computing Systems
Reliability and fault tolerance have become aspects of growing relevance in the field of HPC, due to the increased probability that faults of different kinds will occur in these systems.
Diego Montezanti
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Approximate Triple Modular Redundancy: A Survey
In recent years, approximate computing (AC) has attracted attention owing to its tradeoff between the exactness of computations and performance gains. AC has also been probed for the technique of Triple modular redundancy (TMR). TMR is a well-known fault
Tooba Arifeen +2 more
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Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should
Christopher J. Elash +6 more
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In-Pipeline Processor Protection against Soft Errors
The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher
Ján Mach +2 more
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Assessment of inhalation technique in patients with bronchial asthma and chronic obstructive pulmonary disease [PDF]
Aim. Investigate inhalation techniques using different inhalers types and their effect on the course of disease. Materials and methods. This cross-sectional study included 110 patients with asthma, chronic obstructive pulmonary disease using the ...
Natalia V. Trushenko +6 more
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