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Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism [PDF]

open access: yesFrontiers in Computational Neuroscience, 2023
Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this
Yu Xie   +3 more
doaj   +2 more sources

Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs [PDF]

open access: yesIEEE Access, 2020
Soft-core processors implemented in SRAM-based FPGAs are an attractive option for applications to be employed in radiation environments due to their flexibility, relatively-low application development costs, and reconfigurability features enabling them ...
Server Kasap   +4 more
doaj   +2 more sources

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories [PDF]

open access: yesComputers, 2017
Non-volatile memories (NVMs) offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey
Sparsh Mittal
doaj   +2 more sources

Hybrid Lockstep Technique for Soft Error Mitigation

open access: yesIEEE Transactions on Nuclear Science, 2022
This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer.
M. Pena-Fernandez   +7 more
openaire   +4 more sources

Soft Error Mitigation for SRAM-Based FPGAs [PDF]

open access: yes23rd IEEE VLSI Test Symposium (VTS'05), 2005
FPGA-based designs are more susceptible to single-event up-sets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits.
Ghazanfar Asadi, Mehdi Baradaran Tahoori
openaire   +1 more source

A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection

open access: yesIEEE Access, 2022
Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to the system. Ionizing radiation induced soft error is one of the major concerns in the design of electronic systems, especially in avionics or space ...
Meng Dong   +5 more
doaj   +1 more source

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial

open access: yesSensors, 2021
Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs).
Óscar Ruano   +5 more
doaj   +1 more source

Dynamic Partial Reconfiguration Project for the Anti-single Event Effect Based on the Soft Error Mitigation

open access: yesNantong Daxue xuebao. Ziran kexue ban, 2020
With the wide application of FPGA(field programmable gate array) based on the SRAM(static randomaccess memory) in the aerospace field, the probability of SEU(single event upset) increases gradually while the FPGAs are exposed in irradiation environment ...
XIE Da;DONG Yiping;WANG Lan;CAO Jinde;GUO Junjie
doaj   +1 more source

Enhanced deep soft interference cancellation for multiuser symbol detection

open access: yesETRI Journal, 2023
The detection of all the symbols transmitted simultaneously in multiuser systems using limited wireless resources is challenging. Traditional model-based methods show high performance with perfect channel state information (CSI); however, severe ...
Jihyung Kim, Junghyun Kim, Moon-Sik Lee
doaj   +1 more source

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

open access: yesIEEE Journal of the Electron Devices Society, 2020
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed.
M. Pown, B. Lakshmi
doaj   +1 more source

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