Results 1 to 10 of about 13,512 (161)
Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect [PDF]
Micromachines, 2023 In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device ...
Chenyu Yin +4 more
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Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset [PDF]
Micromachines, 2023 This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally,
Weitao Yang +8 more
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Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell [PDF]
Micromachines, 2023 In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a
Naheem Olakunle Adesina
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Single-Event-Upset Sensitivity Analysis on Low-Swing Drivers [PDF]
The Scientific World Journal, 2014 Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft ...
Nor Muzlifah Mahyuddin, Gordon Russell
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Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset [PDF]
MicromachinesPlanar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses
Hongwei Zhang +6 more
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Soft-Error-Resilient Static Random Access Memory with Enhanced Write Ability for Radiation Environments [PDF]
MicromachinesAs semiconductor technologies advance, SRAM cells deployed in space systems face heightened sensitivity to radiation-induced soft errors. In conventional 6T SRAM, when high-energy particles strike sensitive nodes, single-event upsets (SEUs) may occur ...
Se-Yeon Park, Eun Gyo Jeong, Sung-Hun Jo
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Low power and high-speed quadrate node upset tolerant latch design using CNTFET [PDF]
Scientific ReportsScalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size.
Shaik Asiya, Satheesh Kumar S
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Mitigating bit flips or single event upsets in epilepsy neurostimulators
Epilepsy and Behavior Case Reports, 2016 Objectives: The objective of this study was to review software errors known as single event upsets (SEUs) or bit flips due to cosmic rays in epilepsy neurostimulators. Materials and methods: A case report of a single event upset or bit flip is discussed;
Alice X. Dong +4 more
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Bootstrapped Driver and the Single-Event-Upset Effect [PDF]
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-daloo +3 more
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Fushe yanjiu yu fushe gongyi xuebao, 2021 This study investigates the AD574, a 12-bit analog/digital converter (ADC) produced by American Analog Devices, Inc. (ADI) using bipolar/I2L technology. The test samples are subjected to a total ionizing dose (TID) of 400 Gy(Si) under 60Co γ irradiation.
XIANG Chuanfeng +10 more
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