Results 1 to 10 of about 311 (217)
Bootstrapped Driver and the Single-Event-Upset Effect [PDF]
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-daloo +3 more
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Fushe yanjiu yu fushe gongyi xuebao, 2021 This study investigates the AD574, a 12-bit analog/digital converter (ADC) produced by American Analog Devices, Inc. (ADI) using bipolar/I2L technology. The test samples are subjected to a total ionizing dose (TID) of 400 Gy(Si) under 60Co γ irradiation.
XIANG Chuanfeng +10 more
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Single Event Upset: An Embedded Tutorial [PDF]
21st International Conference on VLSI Design (VLSID 2008), 2008 With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors.
Fan Wang, Vishwani D. Agrawal
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Micromachines, 2023 In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device ...
Chenyu Yin +4 more
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, 2021 In Universe, there are innumeral activities that keep on happening and a lot of effects that are produced as outcomes. One such example is Single Event Upset. SEU is the error generated in the operation performed by a due to the strike between a single ionizing particle like electron, proton or neutron and a sensitive node in micro-electronic device ...
Jilani, Aavesh +2 more
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Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset
Micromachines, 2023 This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally,
Weitao Yang +8 more
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Single event upset reinforcement technology of DICE flip-flop based on layout design
Xibei Gongye Daxue Xuebao, 2022 D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale.
LAI Xiaoling +4 more
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Single-Event Upsets in Microelectronics [PDF]
MRS Bulletin, 2003 AbstractThis article introduces the February 2003 issue of MRS Bulletin on “Single-Event Upsets (SEUs) in Microelectronics.” These radiation effects in devices and circuits have been recognized in recent years as a key reliability concern for many current and future silicon-based technologies.
Henry H.K. Tang, Nils Olsson
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Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications
IEEE Access, 2023 Deep sub-micron memory devices play a crucial role in space electronic applications due to their susceptibility to single-event upset and double-node upset types of soft errors. When a charged particle from space hit a scaled memory circuit, the critical
Pavan Kumar Mukku, Rohit Lorenzo
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Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell
Micromachines, 2023 In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a
Naheem Olakunle Adesina
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