Results 41 to 50 of about 13,512 (161)

Mitigation of Single Event Upset Effects in Nanosheet FET 6T SRAM Cell

IEEE Access
The effects of single event upset (SEU) by alpha particles and heavy ions on the data flip of a 3 nm technology node gate-all-around (GAA) nanosheet field-effect transistor (NSFET) 6T static random-access memory (SRAM) cell was studied through technology
Minji Bang, Jonghyeon Ha, Minki Suh, Dabok Lee, Minsang Ryu, Jin-Woo Han, Hyunchul Sagong, Hojoon Lee, Jungsik Kim   +8 more
doaj   +1 more source

Accelerator simulation test technology and its application for single event effect evaluation in space

He jishu, 2023
BackgroundThe space environment contains numerous high-energy particles, and a single high-energy particle passing through a spacecraft shell bombards the electronic devices within, triggering single-particle effects such as device logic state upset and ...
CHEN Qiming, GUO Gang, SUI Li, LIU Jiancheng, ZHANG Yanwen, ZHANG Fuqiang, YIN Qian, HAN Jinhua, ZHANG Zheng, SUN Haohan   +9 more
doaj   +1 more source

Update of Single Event Effects Radiation Hardness Assurance of Readout Integrated Circuit of Infrared Image Sensors at Cryogenic Temperature

Sensors, 2018
This paper review presents Single Event Effects (SEE) irradiation tests under heavy ions of the test-chip of D-Flip-Flop (DFF) cells and complete readout integrated circuits (ROIC) as a function of temperature, down to 50 K.
Laurent Artola, Ahmad Al Youssef, Samuel Ducret, Franck Perrier, Raphael Buiron, Olivier Gilard, Julien Mekki, Mathieu Boutillier, Guillaume Hubert, Christian Poivrey   +9 more
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Mutual interference induced by single event effects in CMOS circuits

AIP Advances, 2020
Single event effect (SEE) induced mutual interference in CMOS circuits, including single event (SE) induced coupling effects (crosstalk) and modulation in local supply voltage on power-supply rails, was studied based on the increase in metal interconnect
Lili Ding, Wei Chen, Tan Wang, Fengqi Zhang, Yinhong Luo, Guo-Qing Yang   +5 more
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System effects of single event upsets [PDF]

7th Computers in Aerospace Conference, 1989
Single Event Upsets (SEUs) pose a serious threat to computer reliability and longevity. SEU effects are found at sea level, in airborne avionics, and in space. At the system level, SEUs in processors are controlled by replication and voting, watchdog processors, and tagged data schemes.
openaire   +1 more source

Overview of software tools for modeling single event upsets in microelectronic devices

Безопасность информационных технологий, 2016
The paper presents the results of the analysis of existing simulation tools for evaluation of single event upset susceptibility of microelectronic devices with deep sub-micron feature sizes. This simulation tools are meant to replace obsolete approach to
Anatoly Alexandrovich Smolin
doaj  

Understanding radiation effects in SRAM-based field programmable gate arrays for implementing instrumentation and control systems of nuclear power plants

Nuclear Engineering and Technology, 2017
Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems.
T.S. Nidhin, Anindya Bhattacharyya, R.P. Behera, T. Jayanthi, K. Velusamy   +4 more
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A Soft Error Self-Resilience Radiation-Hardened 14T SRAM for Aerospace Applications

IEEE Access
Various charged particles in space threaten memory circuit integrity and dependability, including photons, alpha particles, and high-energy ions outside the Low Earth Orbit region.
Guguloth Anjaneyulu, Asisa Kumar Panigrahy, Mukku Pavan Kumar, Shams Ul Haq, Abdolreza Darabi, Erfan Abbasian, Priyanka Sharma, M. Durga Prakash   +7 more
doaj   +1 more source

Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell

Journal of Electrical and Computer Engineering
The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon-based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET-based SRAM circuit is designed using the look up table-based Verilog
Aishwarya K, Lakshmi B
doaj   +1 more source

Radiation Hardened NULL Convention Logic Asynchronous Circuit Design

Journal of Low Power Electronics and Applications, 2015
This paper proposes a radiation hardened NULL Convention Logic (NCL) architecture that can recover from a single event latchup (SEL) or single event upset (SEU) fault without deadlock or any data loss.
Liang Zhou, Scott C. Smith, Jia Di
doaj   +1 more source