An Updated Perspective of Single Event Gate Rupture and Single Event Burnout in Power MOSFETs
IEEE Transactions on Nuclear Science, 2013Jeffrey L Titus
exaly
Predictors of outcome after single-event multilevel surgery in children with cerebral palsy
Bone and Joint Journal, 2016exaly
Appreciating the effectiveness of single event effect mitigation techniques
2014 IEEE/AIAA 33rd Digital Avionics Systems Conference (DASC), 2014openaire +1 more source
The Effects of Total Ionizing Dose on Single Event Effects
2009Buchner, S. +4 more
openaire +1 more source
Update of Single Event Effects Radiation Hardness Assurance of Readout Integrated Circuit of Infrared Image Sensors at Cryogenic Temperature [PDF]
This paper review presents Single Event Effects (SEE) irradiation tests under heavy ions of the test-chip of D-Flip-Flop (DFF) cells and complete readout integrated circuits (ROIC) as a function of temperature, down to 50 K.
Laurent Artola +9 more
doaj +4 more sources
Study on Single Event Effects of Enhanced GaN HEMT Devices under Various Conditions [PDF]
GaN HEMT devices are sensitive to the single event effect (SEE) caused by heavy ions, and their reliability affects the safe use of space equipment. In this work, a Ge ion (LET = 37 MeV·cm2/mg) and Bi ion (LET = 98 MeV·cm2/mg) were used to irradiate ...
Xinxiang Zhang +11 more
doaj +2 more sources
Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits [PDF]
It has been known that negative feedback loops (internal and external) in a SiGe heterojunction bipolar transistors (HBT) DC current mirrors improve single-event transient (SET) response; both the peak transient current and the settling time ...
Md Arifur R. Sarker +8 more
doaj +2 more sources
Single event effects in carbon nanotube electronics
Recent studies on carbon nanotube (CNT) field-effect transistors (FETs) and integrated circuits (ICs) have shown their potential in radiation tolerance.
Ruhai Liu +9 more
doaj +2 more sources
Bootstrapped Driver and the Single-Event-Upset Effect [PDF]
As VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP)
Mohammed Al-daloo +3 more
openaire +2 more sources

