Results 21 to 30 of about 7,404,371 (262)
Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications
Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation.
Satheesh Kumar S, Kumaravel S
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Highly Reliable Quadruple-Node Upset-Tolerant D-Latch
As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in ...
Seyedehsomayeh Hatefinasab +4 more
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In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space ...
Hong-Geun Park, Sung-Hun Jo
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Single-event upset simulation and detection in configuration memory
Single-event upsets (SEUs) from radiation strikes in configuration memory are potentially catastrophic due to their widespread effects. For field-programmable gate arrays (FPGAs), faults in configuration memory propagate into the implemented logic design
Hezekiah Austin +8 more
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This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs).
Aibin Yan +6 more
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Active Radiation-Hardening Strategy in Bulk FinFETs
In this article, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that ...
Antonio Calomarde +3 more
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Single-event-upset-like fault injection: a comprehensive framework
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0018-9499International audienceAn approach to reproduce radiation ground testing results for the study of microprocessors vulnerability to single event upset (SEU) is described in this ...
Faure, F., Velazco, Raoul, Peronnard, P.
core +1 more source
Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should
Christopher J. Elash +6 more
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ABSTRACT Rates of cancer among adolescents and young adults (AYA), age 15–39 years, are increasing. Consequently, radiation oncologists are treating more AYAs who have diagnoses spanning both pediatric and adult practices. Compared to pediatric and older adult patients, AYAs face a unique set of challenges.
Hesham Elhalawani +7 more
wiley +1 more source
Mechanisms and modeling of single-event upset [PDF]
The basic mechanisms of single-event upset are reviewed, including charge collection in silicon junctions and transistors, and properties of single-event upset in CMOS static random access memory (SRAM) cells.
Dodd, Paul E.
core

