Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset [PDF]
MicromachinesPlanar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses
Hongwei Zhang +6 more
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Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect [PDF]
Micromachines, 2023 In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device ...
Chenyu Yin +4 more
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Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset [PDF]
Micromachines, 2023 This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally,
Weitao Yang +8 more
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Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell [PDF]
Micromachines, 2023 In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a
Naheem Olakunle Adesina
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Single-Event-Upset Sensitivity Analysis on Low-Swing Drivers [PDF]
The Scientific World Journal, 2014 Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft ...
Nor Muzlifah Mahyuddin, Gordon Russell
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Single event upset reinforcement technology of DICE flip-flop based on layout design [PDF]
Xibei Gongye Daxue Xuebao, 2022 D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale.
LAI Xiaoling +4 more
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Soft-Error-Resilient Static Random Access Memory with Enhanced Write Ability for Radiation Environments [PDF]
MicromachinesAs semiconductor technologies advance, SRAM cells deployed in space systems face heightened sensitivity to radiation-induced soft errors. In conventional 6T SRAM, when high-energy particles strike sensitive nodes, single-event upsets (SEUs) may occur ...
Se-Yeon Park, Eun Gyo Jeong, Sung-Hun Jo
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Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]
, 2006 The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Benso, Alfredo +5 more
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Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell [PDF]
Journal of Electrical and Computer EngineeringThe effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon-based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET-based SRAM circuit is designed using the look up table-based Verilog
Aishwarya K, Lakshmi B
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Low power and high-speed quadrate node upset tolerant latch design using CNTFET [PDF]
Scientific ReportsScalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size.
Shaik Asiya, Satheesh Kumar S
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