Results 21 to 30 of about 16,109 (304)

Design and Test of Principle Prototype of Space Single Event Upset Discriminating and Positioning System

open access: yesYuanzineng kexue jishu, 2022
Single event upset (SEU) has always been an important factor affecting the reliability of spacecraft electronic equipment, which can cause anomalies in electronic equipment in orbit, and can result in serious spacecraft failure. In order to master signal
ZHAO Zhendong;TAO Wenze;LI Yancun;CHENG Yi;ZHANG Qingxiang;AN Heng;QUAN Xiaoping;ZHANG Chenguang
doaj  

BRAM implementation of a single-event upset sensor for adaptive single-event effect mitigation in reconfigurable FPGAs

open access: yes, 2022
S.1-8In this paper, we study the performance of a Block RAM (BRAM)-based embedded radiation sensor for adaptive single-event effect mitigation in FPGAs. To achieve this, we designed custom BRAM wrappers to extend the Xilinx BRAM macros with scrubbing and
Mengs, P.   +4 more
core   +1 more source

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

open access: yesIEEE Access, 2023
This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile.
Seyedehsomayeh Hatefinasab   +4 more
doaj   +1 more source

Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

open access: yesJournal of Low Power Electronics and Applications, 2019
Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation.
Satheesh Kumar S, Kumaravel S
doaj   +1 more source

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

open access: yesIEEE Journal of the Electron Devices Society, 2020
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed.
M. Pown, B. Lakshmi
doaj   +1 more source

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

open access: yesIEEE Access, 2022
As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in ...
Seyedehsomayeh Hatefinasab   +4 more
doaj   +1 more source

Low-Power Radiation-Hardened Static Random Access Memory with Enhanced Read Stability for Space Applications

open access: yesApplied Sciences
In space environments, radiation particles affect the stored values of SRAM cells, and these effects, such as single-event upsets (SEUs) and single-event multiple-node upsets (SEMNUs), pose a threat to the reliability of systems used in the space ...
Hong-Geun Park, Sung-Hun Jo
doaj   +1 more source

Single-event upset simulation and detection in configuration memory

open access: yesFrontiers in Space Technologies
Single-event upsets (SEUs) from radiation strikes in configuration memory are potentially catastrophic due to their widespread effects. For field-programmable gate arrays (FPGAs), faults in configuration memory propagate into the implemented logic design
Hezekiah Austin   +8 more
doaj   +1 more source

Active Radiation-Hardening Strategy in Bulk FinFETs

open access: yesIEEE Access, 2020
In this article, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that ...
Antonio Calomarde   +3 more
doaj   +1 more source

Dynamic Robust Single-Event Upset Simulator

open access: yesJournal of Aerospace Information Systems, 2018
This paper presents the dynamic robust single-event upset simulator, which is a novel framework for fault injection on hardware (via onchip debugging) and simulation testbeds (via the SimicsĀ® full-...
Edward Carlisle, Alan D. George
openaire   +1 more source

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