Results 21 to 30 of about 315,481 (343)

Single-Event-Upset (SEU) Awareness in FPGA Routing

2007 44th ACM/IEEE Design Automation Conference, 2007
The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with ...
Shahin Golshan, Eli Bozorgzadeh
openalex   +2 more sources

Monitor of the single event upsets and linear energy transfer of space radiation on the Beidou navigation satellites

Open Astronomy, 2023
The single event effect caused by space heavy ion radiation is one of the important factors affecting the safety and operation of spacecraft on orbit.
Zhang Binquan, Zhang Shenyi, Shen Guohong, Tuo Changsheng, Zhang Xin, Zhang Huanxin, Quan Lin, Tian Chao, Hou Donghui, Zhou Ping, Ji Wentao   +10 more
doaj   +1 more source

Measurements of Single Event Upset in ATLAS IBL

Journal of Instrumentation, 2020
Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent ...
Balbi, G., Barbero, M., Beccherle, R., Bindi, M., Breugnon, P., Butti, P., Cinca, D., Dickinson, J., Ferrere, D., Fougeron, D., Garcia-Sciveres, M., Garcia Pascual, J., Gaudiello, A., Gemme, C., Giangiacomi, N., Hemperek, T., Jeanty, L., Kepka, O., Kocian, M., Lantzsch, K., Liu, P., Martin, C., Mekkaoui, A., Menouni, M., Potamianos, K., Rozanov, A., Takubo, Y., Wensing., M.   +27 more
openaire   +6 more sources

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

Micromachines, 2023
The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE).
Ruxue Yao, Hongliang Lv, Yuming Zhang, Xu Chen, Yutao Zhang, Xingming Liu, Geng Bai   +6 more
doaj   +1 more source

Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact

IEEE Access, 2022
This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel.
Antonio Calomarde, Salvador Manich, Antonio Rubio, Francisco Gamiz   +3 more
doaj   +1 more source

Design and Test of Principle Prototype of Space Single Event Upset Discriminating and Positioning System

Yuanzineng kexue jishu, 2022
Single event upset (SEU) has always been an important factor affecting the reliability of spacecraft electronic equipment, which can cause anomalies in electronic equipment in orbit, and can result in serious spacecraft failure. In order to master signal
ZHAO Zhendong;TAO Wenze;LI Yancun;CHENG Yi;ZHANG Qingxiang;AN Heng;QUAN Xiaoping;ZHANG Chenguang
doaj  

Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs [PDF]

, 2015
Dual- and triple-well bulk CMOS SRAMs fabricated at the 28-nm node were tested using alpha particles and heavy-ions over a range of supply voltages.
Bartz, Brandon, Bhuva, Bharat L., Chatterjee, Indranil, Gupta, Saket, Monzel, Carl, Narasimham, Balaji, Reed, Robert A., Schrimpf, Ronald D., Vedula, Narayana, Wang, Jung K.   +9 more
core   +2 more sources

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

IEEE Access, 2023
This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost profile.
Seyedehsomayeh Hatefinasab, Alfredo Medina-Garcia, Diego P. Morales, Encarnacion Castillo, Noel Rodriguez   +4 more
doaj   +1 more source

Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

Journal of Low Power Electronics and Applications, 2019
Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation.
Satheesh Kumar S, Kumaravel S
doaj   +1 more source

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

IEEE Journal of the Electron Devices Society, 2020
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed.
M. Pown, B. Lakshmi
doaj   +1 more source