Results 221 to 230 of about 114,741 (276)

Design techniques for soft-error mitigation

2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010
In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft-errors, a concern in the past for space applications, became a reliability issue at ground-level. Alpha particles and atmospheric neutrons induce single event upsets (SEU) affecting memory cells, latches and flip-flops, and single event transients ...
openaire   +1 more source

Evaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiation

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
This work analyses the results of applying Triple Modular Redundancy (TMR) to the SHyLoC CCSDS-121 IP, a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 121.0-B-2 lossless compression standard, a universal compressor ...
Antonio J. Sánchez, Y. Barrios, Lucana Santos, R. Sarmiento   +3 more
semanticscholar   +1 more source

Soft error rate mitigation techniques for modern microcircuits

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2003
A unique circuit hardening technique is described, which can totally eliminate both alpha and neutron induced soft errors from deep submicron microcircuits. This hardening technique, termed temporal sampling, addresses both traditional static latch SEUs (single event upsets) as well as SET (single event transient) induced errors.
D.G. Mavis, P.H. Eaton
openaire   +1 more source

Mitigation of Soft Errors in Implantable Medical Devices

2020 7th International Conference on Electrical and Electronics Engineering (ICEEE), 2020
Today, soft errors are one of the major design technology challenges in implantable medical devices (IMDs). IMDs such as pacemakers and implantable cardioverter defibrillators, relying on integrated-circuit technology, are susceptible to soft errors from energetic particles (neutron and alpha particles).
openaire   +1 more source

Circuit-Level Soft-Error Mitigation

2010
In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft errors, a concern in the past for space applications, became a reliability issue at ground level. Alpha particles and atmospheric neutrons induce single-event upsets (SEUs) affecting memory cells, latches, and flip-flops, and single-event transients (
openaire   +2 more sources

A Soft-Error Mitigated Microprocessor With Software Controlled Error Reporting and Recovery

IEEE Transactions on Nuclear Science, 2016
A MIPS 4Kc compliant embedded microprocessor design that incorporates architectural features for software controlled soft-error recovery is presented. The design leverages classical fault tolerance techniques, e.g., error detection and instruction restart, implemented at the micro-architectural level, and added instructions for error recovery.
Chad Farnsworth, Lawrence T. Clark, Anudeep R. Gogulamudi, Vinay Vashishtha, Aditya Gujja   +4 more
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A method for issue queue soft error vulnerability mitigation

2016 17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), 2016
Issue queue is a critical structure in the pipeline and more vulnerable to soft-error strikes. Reducing soft error vulnerability of issue queue cannot be ignored in microprocessor reliability design. Instructions clog in issue queue caused by instruction flow mix and functional unit configuration mismatch.
Liu Tang, Zhangqin Huang
openaire   +1 more source

Soft-Error Characterization and Mitigation Strategies for Edge Tensor Processing Units in Space

IEEE Transactions on Aerospace and Electronic Systems
The Google Coral Edge Tensor Processing Unit (Edge TPU) offers low-power, high-performance capabilities ideal for enabling deep learning in space. However, as a commercial product, no reliability considerations are made in its design.
Tyler Garrett, Seth Roffe, Alan D. George   +2 more
semanticscholar   +1 more source

Exploiting low power circuit topologies for soft error mitigation

2016 IEEE International Reliability Physics Symposium (IRPS), 2016
Alpha particle experimental results for arithmetic circuits implemented using transmission gate logic are shown to have 35% lower soft error rate as well as 30% lower power consumption compared to standard CMOS circuits. Analytical models confirm the experimental trends and help optimize and predict the power-SER trade-off.
Mahatme, N. N., Chatterjee, I., Jagannathan, S., Gaspard, N., Assis, T., Wen, S. J., Wong, R., Bhuva, B. L.   +7 more
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Soft error mitigation through selection of noninvert implication paths

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2014
As transistor feature size scales down, soft errors in combinational logic because of high-energy particle radiation is gaining increasing concerns. In this paper, a soft error mitigation method based on accurate mathematical modeling of SER and addition of non-invert functionally redundant wires (FRWs) is proposed.
Bin Zhou, Srikanthan Thambipillai, Wei Zhang   +2 more
openaire   +1 more source