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Soft error effects analysis and mitigation in VLIW safety-critical applications
2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), 2014VLIW architectures are widely employed in several embedded signal applications since they offer the opportunity to obtain high computational performances while maintaining reduced clock rate and power consumption. Recently, VLIW processors are being considered for employment in various embedded processing systems, including safety-critical ones (e.g ...
SABENA, DAVIDE +2 more
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Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation
2016The analysis in Chap. 8 had shown that decreasing threshold voltages increase the critical charge of logic circuits thus providing more robustness to radiation transients and soft delay effects. In a normal dynamic threshold MOS (DTMOS) scheme, the body-source junction is “forward biased” (at less than 0.6 V), forcing the threshold voltage to drop and ...
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Alpha particle mitigation strategies to reduce chip soft error upsets
Journal of Applied Physics, 2007The continued scaling of complementary metal oxide semiconductor device technologies has lead to continued device shrinkage and decreases in the Vdd, the operating voltage of the device transistors. Scaling has meant denser circuitry overall, thinner silicon (e.g., silicon on insulator) in logic applications, and less charge on capacitors for volatile ...
C. Cabral, K. P. Rodbell, M. S. Gordon
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Experiences with software-based soft-error mitigation using AN codes
Software Quality Journal, 2014Arithmetic error coding schemes are a well-known and effective technique for soft-error mitigation. Although the underlying coding theory is generally a complex area of mathematics, its practical implementation is comparatively simple in general. However, compliance with the theory can be lost easily while moving toward an actual implementation, which ...
Martin Hoffmann +5 more
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BISS: A Built-In SEU Sensor for Soft Error Mitigation
Applied Mechanics and Materials, 2011This paper presents a built-in SEU sensor (BISS) to detect soft errors in CMOS digital systems. BISS detects SEU-induced soft errors by monitoring the meta-stability in the flip-flops. BISS includes positive pulse generator, footed dynamic inverter and keeper. SPICE simulations validate the approach.
Zheng Feng Huang, Mao Xiang Yi
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Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires
IEEE Transactions on Reliability, 2008We introduce a logic-level soft error mitigation methodology for combinational circuits. The proposed method exploits the existence of logic implications in a design, and is based on selective addition of pertinent functionally redundant wires to the circuit.
S. Almukhaizim, Y. Makris
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Design EG-LDPC codes for soft error mitigation in memory
2011 Academic International Symposium on Optoelectronics and Microelectronics Technology, 2011As the feature sizes of integrated circuits decreasing, single event transient (SET) in combinational circuits can not been ignored any longer. In this paper, a novel fault-secure scheme for memory has been proposed by studying the structural features of Euclidean Geometry-Low Density Parity Check (EG-LDPC) codes.
Xiao Li Yi +3 more
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Soft error trends and mitigation techniques in memory devices
2011 Proceedings - Annual Reliability and Maintainability Symposium, 2011As CMOS process technology scales below 100nm, the amount of charge required to upset a gate or memory cell (Q crit ) is decreasing. Therefore, the probability that an energetic particle can generate enough charge to upset a circuit is increasing. Since these single event upsets do not damage the IC, they are called soft errors.
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Transmission Gate (TG) Based Soft Error Mitigation Methods
2016This chapter discusses transmission-gate (TG) based techniques for filtering Single Event Transients (SETs) on logic outputs. After covering the basic TG design and Transient Tunable Filter methodologies, it focuses on a TG mitigation methodology based on “varying gate and body bias control”.
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Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture
2016With the rapid development of integrated circuit technology, soft error has increasingly become the major factor for the reliability of microprocessors. The researchers employ a variety of methods to reduce the influence of soft errors. Besides the lower delay and increasing bandwidth, 3D integration technology also has the ability of heterogeneous ...
Chao Song, Minxuan Zhang
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