Results 251 to 260 of about 6,338 (277)

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007
In this paper, we propose two techniques to mitigate soft error effects on the switch modules of SRAM-based FPGAs: 1) The first technique tolerates SEU-caused open errors based on a new programming method for SRAM-bits of switch modules, and 2) The second technique mitigates SEU-cause short errors in the switch modules based on a mixed programmable and
Zarandi, H., Miremadi, S.G., Dhiraj, Pradhan, Mathew, Jimson   +3 more
openaire   +1 more source

RAT: A Lightweight System-level Soft Error Mitigation Technique

2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 2020
To achieve a substantial reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper proposes a low-cost system-level soft error mitigation technique, which allocates the critical application function to a pool of specific general-purpose processor registers.
Jonas Gava, Ricardo Augusto da Luz Reis, Luciano Ost   +2 more
openaire   +1 more source

ISO26262-compliant soft-error mitigation in register banks

2017 22nd IEEE European Test Symposium (ETS), 2017
Temporary malfunction of ICs is often caused by Single Event Upsets (SEUs). That is why the automotive safety standard ISO 26262 demands measures to detect and mitigate a certain percentage of safety-critical SEUs. Different kinds of modules require different kinds of safety mechanisms. A frequently used module type is the Register Bank, which provides
openaire   +1 more source

Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
We discuss the problem of soft errors in asynchronous burst-mode machines (ABMMs), and we propose two solutions. The first solution is an error tolerance approach, which leverages the inherent functionality of Muller C-elements, along with a variant of duplication, to suppress all transient errors.
Sobeeh Almukhaizim, Feng Shi 0010, Eric Love, Yiorgos Makris   +3 more
openaire   +1 more source

Experiences with software-based soft-error mitigation using AN codes

Software Quality Journal, 2014
Arithmetic error coding schemes are a well-known and effective technique for soft-error mitigation. Although the underlying coding theory is generally a complex area of mathematics, its practical implementation is comparatively simple in general. However, compliance with the theory can be lost easily while moving toward an actual implementation, which ...
Martin Hoffmann 0001, Peter Ulbrich, Christian Dietrich 0001, Horst Schirmeier, Daniel Lohmann, Wolfgang Schröder-Preikschat   +5 more
openaire   +1 more source

Soft Error Mitigation on Dual Rail Latch

Applied Mechanics and Materials, 2016
A single event upset (SEU) or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption.
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Temporal redundancy latch-based architecture for soft error mitigation

2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017
Current transients caused by energetic particle strikes are a serious threat for digital circuits in aerospace applications. Such single-event transients (SETs) can corrupt the circuit state, with possibly devastating consequences. Although it is possible to protect circuits with spatial redundancy techniques, the area and power overhead is high ...
Robert Schmidt 0003, Alberto García Ortiz, Görschwin Fey   +2 more
openaire   +1 more source

Soft-error mitigation by means of decoupled transactional memory threads

Distributed Computing, 2014
CMOS scaling exacerbates hardware errors making reliability a big concern for recent and future microarchitecture designs. Mechanisms to provide fault tolerance in architectures must accomplish several objectives such as low performance degradation, power consumption and area overhead.
Daniel Sánchez 0004, Juan M. Cebrian, José M. García 0001, Juan L. Aragón   +3 more
openaire   +1 more source

Framework for Selective Flip-Flop Replacement for Soft Error Mitigation

2015 28th International Conference on VLSI Design, 2015
With increasing adoption of newer technologies and architectures targeted for automotive and aviation electronics with an objective to improve performance and/or reduce power/area, soft-error robustness is becoming an important issue to ensure reliable operation for an extended lifetime over a wide range of operating conditions.
Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti 0001   +2 more
openaire   +1 more source

In-place LUT polarity inVersion to mitigate soft errors for FPGAs

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016
In-place Polarity inVersion (IPV) has been proposed to mitigate the single event upset (SEU) induced soft errors for academic VPR FPGA architectures, and this paper extends the original IPV so that it can be used for commercial FPGA architectures. Different from the original IPV, we use a new soft error model based on signal probability and propose a ...
Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He   +3 more
openaire   +1 more source