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Invited - Cross-layer approaches for soft error modeling and mitigation
Proceedings of the 53rd Annual Design Automation Conference, 2016Radiation-induced soft errors are major reliability threat for VLSI systems fabricated using nanoscale technologies. While soft errors are generated due to device-level interactions, they could propagate at multiple levels and impair user-visible outputs.
Ebrahimi, Mojtaba, Tahoori, Mehdi B.
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Optimal soft error mitigation in wireless communication using approximate logic circuits
Sustainable Computing: Informatics and Systems, 2021Joseph Henry Anajemba +2 more
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Static analysis to mitigate soft errors in register files
2009 Design, Automation & Test in Europe Conference & Exhibition, 2009Jongeun Lee, Aviral Shrivastava
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RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique
IFIP Advances in Information and Communication Technology, 2021Jonas Gava, Ricardo Reis, Luciano Ost
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Soft error mitigation in asynchronous networks on chip.
2012In advanced deep submicron technologies, the aggressive scaling of the clock to increasingly higher frequencies has now terminated. At the circuit top level, global clocking is not feasible anymore, which has led to the popularization of the Globally Asynchronous Locally Synchronous paradigm for constructing complex system on chip devices, with local ...
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Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs
IEEE Transactions on Computers, 2012Naga Durga Prasad Avirneni +1 more
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Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires
IEEE Transactions on Reliability, 2008Yiorgos Makris, Sobeeh Almukhaizim
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Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007Hossein Asadi, Mehdi B Tahoori
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