Results 131 to 140 of about 37,708 (227)

The High-Energy Ion Telescope (HIT) for the Interstellar Mapping And Acceleration Probe (IMAP) Mission. [PDF]

Space Sci Rev
Christian ER, Mitchell JG, Bruno A, Albaijes D, Bailey Newman S, Boggs RC, Choi MK, Cohen CMS, Cook WR, Darwish YS, Davis AJ, de Nolfo GA, Dumonthier JJ, Garnett RD, Gkioulidou M, Gregory KJ, Guzman Garcia D, Haas JP, Hollenhorst C, Jeunon M, Kaiser MA, Kanekal SG, Kecman B, Leske RA, Letzer JD, Liceaga Indart I, McComas DJ, McNeel B, Muro GD, Nolan JT, Ogindo M, Petrowich P, Reaves WJ, Rosnack TP, Saghafi N, Salerno CL, Schwadron NA, Silber MA, Smith ES, Smith MT, Suárez G, Tatoli T, Tiu CP, Wiedenbeck ME, Windhausen MH, Xu Z.   +45 more
europepmc   +1 more source

OmBNNet: a resource-efficient FPGA-based obfuscated malware detection method using binarized neural network. [PDF]

Sci Rep
Das K, Borah BB, Bhattacharyya DK, Kalita J.   +3 more
europepmc   +1 more source

Test methodology for SRAM based FPGAs. [PDF]

, 2018
openaire   +1 more source

DA-FIS: A high-speed dynamic adaptive fault injection server framework for reliable FPGA-based embedded systems. [PDF]

PeerJ Comput Sci
Alhayan F, Kaur G, Alanazi S, Rehman MB, Mansouri W, Albalawneh D, Alqazzaz A, Alkhudhayr H.   +7 more
europepmc   +1 more source

A single event transient detector in SRAM-based FPGAs

IEICE Electronics Express, 2017
Xu, Xiumin, Liang, Huaguo, Huang, Zhengfeng, Jiang, Cuiyun, Lu, Yingchun, Yan, Aibin, Ni, Tianming, Yi, Maoxiang   +7 more
openaire   +2 more sources

An energy efficient processor array and memory controller for accurate processing of convolutional neural network-based inference engines. [PDF]

Sci Rep
Deepika S, Arunachalam V.
europepmc   +1 more source

DEX in near Earth orbit in light of Venus Orbiter Dust Experiment. [PDF]

Sci Rep
Pabari J, Nambiar S, Singh R, Jitarwal S, Bhardwaj A, Praneeth SMK, Shah B, Suthar P, Pandya S, Rami J, Kumar D, Singh VK, Khandekar R, Singh RK, Sahu A, Adalja H, Patel A.   +16 more
europepmc   +1 more source

Novel structures of chaos-based parallel multiple image encryption and FPGA implementation. [PDF]

Sci Rep
Hoang TM, Anh PQ, Hoang MH, Tran DQ, Assad SE.   +4 more
europepmc   +1 more source

Power-efficient hardware architecture for 2-D multiple transforms in VVC. [PDF]

Sci Rep
Palagani MB, Nalluri P.
europepmc   +1 more source

Hardware Accelerators for Cardiovascular Signal Processing: A System-on-Chip Perspective. [PDF]

Micromachines (Basel)
Hariri R, Cirstea M, Oghaz MMD, Benkrid K, Faust O.   +4 more
europepmc   +1 more source