Results 111 to 120 of about 37,708 (227)
Efficient architectures and power modelling of multiresolution analysis algorithms on FPGA
, 2011 This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In the past two decades, there has been huge amount of interest in Multiresolution Analysis Algorithms (MAAs) and their applications.
Sazish, Abdul Naser
core
High performance FPGA implementation of the mersenne twister
, 2008 Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twister is presented. The proposed architecture has the smallest footprint of all
Shrutisagar Chandrasekaran +3 more
core +1 more source
Efficient FPGA implementation and power modelling of image and signal processing IP cores
, 2007 This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer ...
Chandrasekaran, Shrutisagar
core
Configuration Sharing Optimized Placement and Routing
Reconfigurable systems have been shown to achieve very high computational performance. However, the overhead associated with reconfiguration of hardware remains a critical factor in overall system performance.
Cobb, Jonathan E., Stepien, Piotr
core +1 more source
Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA
, 2010 International audienceIn order to increase reliability and availability of Static-RAM based field programmable gate arrays (SRAM-based FPGAs), several methods of tolerating defects and permanent faults have been developed and applied.
Farid Lahrach +7 more
core +1 more source
Discover ElectronicsThe rapid growth of the Internet of Things (IoT) and wearable healthcare devices has intensified the need for ultra-low-power Very Large Scale Integration (VLSI) designs that can operate reliably under changing and often unpredictable workloads ...
Ashish Pasaya +2 more
doaj +1 more source
, 2013 This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software-based techniques combined with a nonintrusive hardware module. We implemented a MIPS-based soft-core processor in a Virtex5 FPGA and hardened it with software- and ...
Quinn, Heather +7 more
core +1 more source
Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection
, 2008 International audienceThis paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results
Foucard, G. +13 more
core +1 more source
FPGA-based operational concept and payload data processing for the Flying Laptop satellite
, 2009 Flying Laptop is the first small satellite developed by the Institute of Space Systems at the Universität Stuttgart. It is a test bed for an on-board computer with a reconfigurable, redundant and self-controlling high computational ability based on the ...
Huber, Felix +5 more
core
A compressed sensing neuromorphic processor for sparse signal classification. [PDF]
Front NeurosciQian L +7 more
europepmc +1 more source