Results 51 to 60 of about 115 (112)

A Review of Performance and Reliability Issues in D Flip‐Flops for Future Artificial Intelligence and Internet of Things Applications

IET Circuits, Devices &Systems, Volume 2025, Issue 1, 2025.
In this paper, various D flip‐flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional‐bridging FF (CBFF)‐S, self‐shut‐off pulsed ...
Syeda Hurmath Juveria, R. Shashank, J. Ajayan, Amit Krishna Dwivedi, D. Nirmal, Shashikant Patil   +5 more
wiley   +1 more source

Synchronisation, Optimisation and Adaptation of Machine Learning Techniques for Computer Vision in Cyber‐Physical Systems: A Comprehensive Analysis

IET Cyber-Physical Systems: Theory &Applications, Volume 10, Issue 1, January/December 2025.
This systematic analysis aims to offer a unique point to researchers and facilitates this process by allowing researchers to benchmark and compare various techniques, evaluate their effectiveness and establish best practices. It provides evidence‐based insights into optimal strategies for implementation while addressing potential trade‐offs in ...
Kai Hung Tang, Mohamed Chahine Ghanem, Pawel Gasiorowski, Vassil Vassilev, Karim Ouazzane   +4 more
wiley   +1 more source

Enhanced Soft Error Rate Estimation Technique for Aerospace Electronics Safety Design via Emulation Fault Injection

Applied Sciences
In this paper, we propose Automatic Configuration Memory Fault Injection (ACMFI), a tool that calculates the architectural vulnerability factor (AVF) and soft error rate (SER) using the emulation fault injection technique. SER, which is essential for the
Dongmin Lee, Taehyeong Nam, Daeseon Park, Yeju Kim, Jongwhoa Na   +4 more
doaj   +1 more source

Test methodology for SRAM based FPGAs. [PDF]

, 2018
openaire   +1 more source

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Defect tolerant SRAM based FPGAs

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
We propose a new approach to redundancy for field programmable gate arrays (FPGAs) which uses a novel reconfiguration network. Modifications are made to the wiring segments and a spare element is incorporated at the end of each row. By using the technique it will be possible to construct arrays 10 times larger than are commercially economic at present.
Jason L. Kelly, Peter A. Ivey
openaire   +1 more source

A fault injection tool for SRAM-based FPGAs

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 2004
A fault injection tool for SRAM-based FPGAs based on the fault emulation technique is presented. Faults are injected by modifying the configuration bitstream while this is loaded into the device, without using standard synthesis tools or available commercial software, such as Jbits or similar.
Monica Alderighi, Sergio D'Angelo, Marcello Mancini, Giacomo R. Sechi   +3 more
openaire   +2 more sources

An SRAM-based FPGA architecture

Proceedings of Custom Integrated Circuits Conference, 2002
An SRAM-based FPGA architecture has been developed using a licensed AT6000 architecture base. The logic-cell architecture exploits an efficient, medium-grained, fixed library cell that implements most frequently used synthesis functions. An internal routing structure enables dense designs using a highly connected grid-based routing system and a ...
S. Gould, B. Worth, K. Clinton, E. Millham, F. Keyser, R. Palmer, S. Hartman, T. Zittritsch   +7 more
openaire   +1 more source

On the reliability evaluation of sram-based FPGA designs

International Conference on Field Programmable Logic and Applications, 2005., 2005
Benefits of field programmable gate arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate the reliability of the FPGA, because of their high susceptibility to soft errors, which are due to the high density of embedded SRAM cells.
Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich   +2 more
openaire   +1 more source

An automated test framework for SRAM-based FPGA

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
An automated test framework for SRAM-based FPGA is presented. With the framework, test configurations of different categories can be partially or completely generated, and the tests be running using the generated configurations. Data driven design provides the test framework the flexibility of change the user interface and the command line arguments ...
Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang   +3 more
openaire   +1 more source

Power estimation approach for SRAM-based FPGAs

Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000
This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family.
Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel   +4 more
openaire   +1 more source