Results 71 to 80 of about 115 (112)

Fault management techniques for systems with SRAM-based FPGAs

2022
Las Field-Programmable Gate Arrays (FPGAs) SRAM se construyen sobre una memoria de configuración de tecnología RAM Estática (SRAM). Presentan múltiples características que las hacen muy interesantes para diseñar sistemas empotrados complejos. En primer lugar presentan un coste no-recurrente de ingeniería (NRE) bajo, ya que los elementos lógicos y de ...
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SRAM-based FPGA's: testing the LUT/RAM modules

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 2002
This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes.
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian   +3 more
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Testing the Local Interconnect Resources of SRAM-Based FPGA's

Journal of Electronic Testing, 2000
This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs. First, it is demonstrated that a n address bit Configurable Interface Multiplexer requires N e 2n test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian   +3 more
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Designing fault tolerant systems into SRAM-based FPGAs

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003
This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy (TMR) has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications.
Fernanda Lima 0001, Luigi Carro, Ricardo Augusto da Luz Reis   +2 more
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A novel fault tolerant approach for SRAM-based FPGAs

Proceedings 1999 Pacific Rim International Symposium on Dependable Computing, 2003
This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming.
Jian Xu, Paifa Si, Wei-Kang Huang, Fabrizio Lombardi   +3 more
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Testing carry logic modules of SRAM-based FPGAs

Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, 2002
The carry logic module (CLM) is an integral part of a configurable logic block (CLB) in a Xilinx XC4000 field programmable gate array (FPGA). This paper addresses the testing issues of a CLM for the first time. The integrity of a CLM is validated by the integrity of all its components.
Xiaoling Sun, Jian Xu, Pieter M. Trouborst   +2 more
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Diagnosing single faults for interconnects in SRAM based FPGAs

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999
This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used.
Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi   +3 more
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Cost-efficient of a cluster in a mesh SRAM-based FPGA

2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014
This paper presents a cost-efficient Built-In Self-Test (BIST) scheme for fault detection and diagnosis of a cluster in a mesh FPGA. In this scheme, test cost reduction is achieved by simultaneous testing of logic and intra-cluster interconnect resources without degradation of diagnostic resolution.
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel   +2 more
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Criticality-aware scrubbing mechanism for SRAM-based FPGAs

2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014
Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA.
Rui Santos, Shyamsundar Venkataraman, Anup Das 0001, Akash Kumar 0001   +3 more
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An analytical delay model for SRAM-based FPGA interconnections

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999
In an SRAM-based FPGA, MOS transistors connect wire segments to construct interconnections between CLBs, resulting in large and unpredictable path delays. So it is necessary to be able to estimate interconnection delays quickly and accurately in order that performance-driven layout and analysis algorithms can achieve high quality. Because the effective
Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang   +3 more
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