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Ultralow Power System-on-Chip SRAM Characterization by Alpha and Neutron Irradiation
IEEE Transactions on Nuclear Science, 2021The static random access memory (SRAM) of an ultralow power system-on-chip (SoC) was tested for single-event upsets (SEUs) using alpha particles and neutron beam sources. The measurements are compared to those of an SRAM-based field-programmable gate array (FPGA), built on a similar technology node. The results reveal opposite trends in the two devices
Avner Haran +12 more
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Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019Space applications constantly require integration of more processing capabilities and greater memory capacity, at reduced weight and power consumption. The IHP 130 nm technology is a commercially-qualified and radiation-assessed technology which is sufficiently aggressive for the conservative approach in the space area.
Aleksandar Simevski +3 more
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Accelerating volume rendering using an on-chip SRAM occupancy map
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2002One of the most severe problems for ray casting architectures is the waste of computation cycles and I/O bandwidth, due to redundant sampling of empty space. While several techniques exist for software implementations to skip these empty regions, few are suitable for hardware implementation. The few which have been presented either require a tremendous
Michael Meißner +3 more
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Providing Root of Trust for ARM TrustZone using On-Chip SRAM
Proceedings of the 4th International Workshop on Trustworthy Embedded Devices, 2014We present the design, implementation and evaluation of the root of trust for the Trusted Execution Environment (TEE) provided by ARM TrustZone based on the on-chip SRAM Physical Unclonable Functions (PUFs). We first implement a building block which provides the foundations for the root of trust: secure key storage and truly random source. The building
Shijun Zhao +4 more
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Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012Scaling of device sizes has reduced gate oxide thickness to a few atomic layers, increasing the vulnerability of the gate oxide to breakdown. During breakdown, devices go through a gradual wearout process characterized by increased leakage. Using experimentally verified gate oxide breakdown models, a detailed analysis of the effect of progressive gate ...
Fahad Ahmed, Linda Milor
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Precharged sram cell for ultra low-power on-chip cache
2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics, 2005This paper proposes an ultra low-power technique to reduce dynamic and leakage power in SRAM. At write mode, the technique reduces the voltage swing required on the bit lines and depends on the cell itself to amplify the small swing to full swing. HSPICE simulation shows 94.2% write power saving in 0.18nm technology.
Ramy E. Aly, Magdy A. Bayoumi
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A 5V-only single chip microcomputer with nonvolatile SRAM
1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1984An 8b single chip microprocessor with a memory containing 32Kb of ROM, 512b of RAM and 512b of nonvolatile SRAM, implemented in 4μm double poly floating gate technology, will be described.
P. Rosini, R. Finaurini, M. Gaibotti
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Immunity Evaluation of SRAM Chips for SOI and SI Technology
2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2019This paper mainly studies the electromagnetic immunity of two kinds of static random access memory (SRAM) chips using bulk silicon (SI) and insulator silicon (SOI) technologies respectively, and the effect of temperature on chip immunity. Direct power injection (DPI) method was used to test the immunity of each functional pin of the two chips, and the ...
Xujing Wu +7 more
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On-line monitoring of system health using on-chip SRAMs as a wearout sensor
2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017Safety critical systems need methodologies for chips to monitor their health in the field, so that the need for repairs can be determined during scheduled maintenance. Prior work provides health monitoring via detection of degradation. Since many wearout mechanisms provide no degradation signal, this paper proposes to use the embedded SRAM as a dynamic
Woongrae Kim, Taizhi Liu, Linda Milor
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Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry
26th IEEE VLSI Test Symposium (vts 2008), 2008In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures.
Niladri Narayan Mojumder +4 more
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