Results 121 to 130 of about 546 (170)

BIST method of SRAM for network-on-chip

2015 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI), 2015
Network-on-chip (NoC) is becoming promising communication architecture for the next-generation system on chips. Intellectual property (IP) core is an important part of NoC system, this paper puts SRAM as an IP core to complete the test study of SRAM. We present a Built-in self-test (BIST) method for SRAM of network-on-chip based on reusing network-on ...
null Xu Chuanpei, null Tao Yi, null Wan Chunting   +2 more
openaire   +1 more source

On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016
This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available.
Pankaj Verma, Rohit Halba, Hemant Patel, Maryam Shojaei Baghini   +3 more
openaire   +1 more source

Challenging on-chip SRAM security with boot-state statistics

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2017
On-chip memory is regarded by most secure system designers as a safe memory space, beyond the eyes of all but the most sophisticated attackers. Once a value is overwritten or the power has been removed, it is assumed that the data stored inside fully ceases to persist.
Joseph McMahan, Weilong Cui, Liang Xia, Jeff Heckey, Frederic T. Chong, Timothy Sherwood   +5 more
openaire   +1 more source

Experimental fault analysis of 1 Mb SRAM chips

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125), 2002
Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that I/sub dd/=4.5 I; temperature=70/spl deg/C, and load capacity C/sub L/=30 pF,
Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki   +2 more
openaire   +1 more source

Unclonable key Generator Based on Chip signature and SRAM-PUF of ATmega328P chip

2018 28th International Conference on Computer Theory and Applications (ICCTA), 2018
Embedded devices are now taking over the world, their presence in everyone's pocket and home arouses questions around privacy and security concerns. What amplifies these concerns are the rapid spread of internet of things (IOT) devices and smart meters across the world.
Amr Elmestekawi, Ashraf Tammam, Hanady Hussien Issa   +2 more
openaire   +1 more source

Self-Repairing SRAM Using On-Chip Detection and Compensation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die V t variations on SRAM read and write failures.
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy 0001   +4 more
openaire   +1 more source

Chip-on-chip technology with copper through-plug for 0.15 μm SRAM

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2004
SRAM reliability impact and MOSFET electrical characteristics with copper (Cu) through-plug for three-dimensional (3-D) integration are examined and some degradation modes are inspected. Although the initial chip yield of chip-on-chip (COC) sample is comparable to references, the degradation occurs after high-temperature-storage (HTS) test.
M. Matsuo, K. Kasai, Y. Okayama, K. Ishimaru, N. Matsunaga, H. Yamaguchi, N. Otsuka, N. Hayasaka   +7 more
openaire   +1 more source

A 256K SRAM with on-chip power supply conversion

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987
A 47.2mm2SRAM utilizing an on-chip power supply conversion and allowing full synchronous operation at either 5.0V or 3.3V pin voltage without performance penalty will be discussed. The chip with a six-device cell size of 109μm2has been built in a 0.7μm CMOS DRAM technology with silicides and double level metal.
A. Roberts, J. Dreibelbis, G. Braceras, J. Gabric, L. Gilbert, R. Goodwin, E. Hedberg, T. Maffitt, L. Meuniar, D. Moran, null Phuong Nguyen, D. Reed, D. Reismiller, R. Sasaki   +13 more
openaire   +1 more source

On-Chip VDC Circuit for SRAM Power Management

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007
Leakage current becomes the dominant factor for contributing to the static power consumption. Power management technique is then required to bring down the power consumption. One of the most effective methods is to reduce the power supply voltage in the standby mode or in the power down active mode.
C.F. Lee, Wesley Lin, F.S. Lai, S.C. Lin
openaire   +1 more source

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

2012 13th Latin American Test Workshop (LATW), 2012
Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime.
Arthur Ceratti, Thiago Copetti, Letícia Maria Veiras Bolzani, Fabian Vargas 0001   +3 more
openaire   +1 more source