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Sparse Convolution FPGA Accelerator Based on Multi-Bank Hash Selection. [PDF]
Micromachines (Basel)Xu J, Pu H, Wang D.
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An SRAM Test Quality Improvement Method For Automotive chips
2021 IEEE International Test Conference in Asia (ITC-Asia), 2021Junlin Huang
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Design and test of an SRAM chip
2013 IEEE 10th International Conference on ASIC, 2013A fully customized 8×8 bits SRAM chip, based on Chartered 0.35 um EEPROM CMOS technology, is designed and taped-out for low-power and low-cost electronic equipment. According to test results, when the supply voltage is 3.3 V and clock frequency is 20 MHz, the chip can work correctly, and the performance reaches the design specifications, the access ...
Wenbin Liu +4 more
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A chip-stacked memory for on-chip SRAM-rich SoCs and processors
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009Advanced SoC chips used in multimedia devices such as mobile phones have a number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a
Hideaki Saito +8 more
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An on-chip test scheme for SRAMs
Proceedings of IEEE International Workshop on Memory Technology, Design, and Test, 2002Semiconductor technology continues to progress dramatically. With the increasing density, the testing of RAM chips has become progressively more difficult. In this paper, a new approach to simplify the testing of large SRAMs (static RAMs), embedded in VLSI chips or as stand-alone chips, by incorporating additional circuitry is proposed. >
P.K. Lala, A. Walker
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SRAM-Based Unique Chip Identifier Techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells.
Srivatsan Chellappa, Lawrence T. Clark
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An on-chip circuit for timing measurement of SRAM IP
2017 IEEE 12th International Conference on ASIC (ASICON), 2017The timing of silicon IPs should be measured before they are integrated into chips. Embedded solutions are needed for timing measurement of silicon IPs. This paper introduces a circuit design for timing measurement of SRAM IP. A new circuit is designed for the measurement of setup time, hold time and access time.
Xianjie Long +3 more
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An On-Chip Sensor to Monitor NBTI Effects in SRAMs
Journal of Electronic Testing, 2014The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime.
Arthur Ceratti +4 more
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A scheme for multiple on-chip signature checking for embedded SRAMs
Proceedings European Design and Test Conference. ED & TC 97, 2000Embedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an embedded memory poses a challenge to a system test engineer, due to its limited controllability and observability.
Mohammed Fadle Abdulla +2 more
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