A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router
, 2022 Jinzhi Lai, Jueping Cai, Jie Chu
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A Reactive and On-Chip Sensor Circuit for NBTI and PBTI Resilient SRAM Design [PDF]
, 2020 Nandakishor Yadav +3 more
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MCAIMem: a Mixed SRAM and eDRAM Cell for Area and Energy-efficient on-chip AI Memory [PDF]
, 2023 Duy-Thanh Nguyen +3 more
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Monitoring time domain characteristics of Parkinson's disease using 3D memristive neuromorphic system. [PDF]
Front Comput Neurosci, 2023 Siddique MAB, Zhang Y, An H.
europepmc +1 more source
On-board processing satellite network architecture and control study [PDF]
The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures.
Campanella, S. Joseph +2 more
core +1 more source
Write‐variation aware alternatives to replace SRAM buffers with non‐volatile buffers in on‐chip interconnects [PDF]
, 2019 Khushboo Rani, Hemangee K. Kapoor
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Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications
, 2018 Sunil Kumar Ojha +3 more
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Effects of cosmic rays on single event upsets [PDF]
Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space.
Fogarty, T. N. +4 more
core +1 more source
FPGA implementation of the BIST intellectual property core for SRAM chips on the board [PDF]
, 2008 Mohamed H. El-Mahlawy +3 more
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