Structural Testing of Modern Reconfigurable Chips
, 2003 International audienceThis paper presents recent developments for testing SRAM-based FPGAs using a structural approach. The specific architecture of these new chips is first presented identifying the specific FPGA test problems as well as the FPGA test ...
Renovell, Michel
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Monitoring time domain characteristics of Parkinson's disease using 3D memristive neuromorphic system. [PDF]
Front Comput Neurosci, 2023 Siddique MAB, Zhang Y, An H.
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Semiconductor microelectronics integrated circuits (ICs) are increasingly integrated into modern life-critical applications, from intelligent infrastructure and consumer electronics to the Internet of Things (IoT) and advanced military and medical ...
Singh, Harshdeep
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A Simulation-Based Methodology for SRAM Defect Analysis and Diagnosis
, 2008 We propose a methodology for systematically injecting defects into an SRAM and simulating the effects. The detectto-fault mapping tables can be constructed after the simulation.
Rei-fu Huang +4 more
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A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
, 2012 [[abstract]]A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work,
Wu, Tsung-Yi; Chen, Kuang-Yao; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern
core
Design and Analysis of Robust Variability-Aware SRAM to Predict Optimum Access-Time to Achieve Yield Enhancement in Future Nano-Scaled CMOS. [PDF]
, 2012 Design variability due to inter-die (D2D) and intra-die (WID) process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance chips in future process technology generations.
Samandari-Rad, Jeren
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Blockchain, Artificial Intelligence, and Cyber Defense on Sensor Networks. [PDF]
Sensors (Basel)Watanabe H.
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SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction. [PDF]
Micromachines (Basel)Li T, Tian J, Qi J.
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A Low-Offset Sense Amplifier with Self-Adaptive Calibration and Dynamic Body-Biased Mitigation Technology for Enhanced SRAM Read Performance. [PDF]
Micromachines (Basel)Liu Y, Hu Y, Xiao H, Liu Y, Chen J.
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A compressed sensing neuromorphic processor for sparse signal classification. [PDF]
Front NeurosciQian L +7 more
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