Results 81 to 90 of about 855 (207)

CMOS Buffer Design Approach for Low Power and Lower Delay SRAM Design

, 2016
Leakage power dissipation of on-chip SRAM constitutes a significant amount of the total chip power consumption in microprocessors and System on chips. With technology scaling, it is becoming increasingly challenging to maintain the yield while attempting
Aswathy, N., Mariyamol, p.p.
core   +1 more source

Different SRAM Cells Using Low Power Reduction Techniques

, 2014
With increasing technology, usage of SRAM Cells has been increased to large extent while designing the system on-chips in CMOS technology. Power consumption and the speed are the major factors of concern for designing a chip along with the leakage power.
Grover, Neeti, Kaur, Navdeep, Grover, Amit, Kaur, Manpreet   +3 more
core  

Error resilient techniques for storage elements of low power design

, 2013
Over two decades of research has led to numerous low-power design techniques being reported. Two popular techniques are supply voltage scaling and power gating.
Yang, Sheng
core  

Fast Statistical Analysis of Rare Failure Events for SRAM Circuits in High-Dimensional Variation Space

, 2018
SRAM (static random-access memory) has been widely embedded in a large amount of semiconductor chips. Therefore, the yield of most semiconductor chips is dominated by the yield of SRAM. SRAM consists of a considerable number of replicated components (e.g.
Shupeng Sun (6068448)
core   +1 more source

Design and Implementation of SRAM-Based Anti-Noise PUF Device Authentication Circuit

, 2023
In today's era, smart electronic products that we use every day are closely related to chips. Daily life is also closely linked to various smart devices with centralized management, such as the Internet of Things, smart homes, health monitoring, self ...
Zhang, Yao-Song
core  

Sram Tabanlı Cihazlarda 2-boyutlu Eg-ldpc Kodlarından Yararlanılarak Uzay’ın Radyasyon Ortamından Kaynaklanan Geçici Hatalara Karşı Koruma Sağlanması

, 2016
div _mce_tmp="1">Bu tez çalışmasında uzay sistemleri elektronik donanımlarında yer alan SRAM tabanlı belleklerde uzayın radyasyon ortamı nedeniyle görülebilecek geçici hatalara karşı korunma sağlayan yeni yöntemler önerilmektedir.
Demirci, Mustafa
core  

Large-Scale Variability Characterization and Robust Design Techniques for Nanoscale SRAM [PDF]

, 2009
Continued increase in the process variability is perceived to be a major roadblock for future technology scaling. Its impact is particularly pronounced in large memory arrays due to both the utilization of minimum sized transistors and their extremely ...
Guo, Zheng
core  

Application of FIB/SEM and TEM to Bit Failure Analyses in SRAM Arrays

, 2003
Many microelectronic chips contain embedded memory arrays. A single SRAM bit-cell contains several transistors. Failure of any of the transistors makes the entire bit-cell inoperable.
Alex Volinsky, Lorraine Johnston, Wentao Qin, David Theodore, Larry Rice   +4 more
core   +1 more source

Design of an SRAM-based physical unclonable function system

, 2015
Safety has been a critical concern in traditional data protection schemes. Placing the secret key in non-volatile memory makes protecting the key difficult and expensive if not impossible. Physical Unclonable Function (PUF) is an emerging primitive based
Liu, Chao Qun
core  

A built-in self-test scheme with diagnostics support for embedded SRAM

, 2012
[[abstract]]In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system.
Chih-Wea Wang;Chi-Feng Wu;Jin-Fu Li;Cheng-Wen Wu;Teng, T.;Chiu, K.;Hsiao-ping Lin
core   +1 more source