Results 71 to 80 of about 855 (207)
Impact of Orientation on the Bias of SRAM-Based PUFs
This paper investigates the impact of memory orientation on the bias pattern of SRAM-based PUFs. We designed and fabricated a 65nm CMOS chip that contains eleven SRAM macros that exercise different memory- and chip-level parameters.
Abideen, Zain Ul +4 more
core
Development of a Through-Stack-Via Integrated SRAM Module
In this paper, a through-stack-via integration process for SRAM module was developed using wafer level pre-patterned BCB bonding. A SRAM module with a built-in decoder has been designed according to this integration process.
Zhong, Xiao +31 more
core +1 more source
Apart from performance and power efficiency, security is another critical concern in the modern memory sub-system design. SRAM, which is routinely used as a data preservation component, has now been developed into an effective primitive known as Physical
Chang, Chip-Hong +7 more
core +1 more source
Method for Improving the Reliability of SRAM-Based PUF Using Convolution Operation
This paper introduces a novel and efficient physical unclonable function (PUF) extraction method for SRAM. The proposed one-layer convolution scheme is based on a convolution operation, which significantly enhances the reliability of the PUF.
Niansong Mei, Qian Lian, Ruihu Cao
core +1 more source
Dual Threshold Voltage SRAM & BIST Comparators
Since the invention of SRAM (Static Random Access Memory), many improvements have been proposed. The major targets are speed, area, and power consumption.
Lee, Po-Ming
core
A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing
An energy-efficient analog SRAM (A-SRAM) is proposed to eliminate redundant analog-to-digital (A/D) and digital-to-analog (D/A) conversion in mixed-signal systems, such as neuromorphic chips and neural networks. D/A conversion is integrated into the SRAM
Dongjoo Shin +7 more
core +1 more source
As the development of microelectronics technology, the design of memory cell has already become an important embranchment in today’s semiconductor design.
Chen, Jiahuan
core
A built-in self-test and self-diagnosis scheme for embedded SRAM
[[abstract]]Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible.
C.-W. Wang;C.-F. Wu;J.-F. Li;C.-W. Wu;T. Teng;K. Chiu;H.-P. Lin
core +1 more source
Single-Chip Motes and SRAM PUF: Feasibility Study
Physically unclonable functions (PUFs) are used as low-cost cryptographic primitives that extract key material from manufacturing variabilities of a device. All microcontrollers have on-chip SRAM; the power-up state of SRAM cells provides one way of obtaining a random output. However, not every SRAM can be used as a PUF.
Faour, Sara +6 more
openaire +3 more sources
Ultra-Low Power and Reliable SRAM for Systems-on-Chip [PDF]
The number of ubiquitous sensors has increased to more than double the human population and is expected to continue growing in the future. The pervasive use of sensors for applications such as personal healthcare and the Internet of Things (IoT) presents a growing sustainability challenge concerning the availability and accessibility of power sources ...
openaire +1 more source

