Results 51 to 60 of about 10,751 (237)
, 2014 Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic
Chandel, Rajeevan +2 more
core +1 more source
SRAM has no chill: exploiting power domain separation to steal on-chip secrets [PDF]
, 2022 Jubayer Mahmod, Matthew Hicks
openalex +1 more source
Advanced Electronic Materials, EarlyView.ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez +10 more
wiley +1 more source
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing [PDF]
, 2008 In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques ...
Acosta Jiménez, Antonio José +8 more
core
Advanced Intelligent Discovery, EarlyView.Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
Low-power adiabatic 9T static random access memory
The Journal of Engineering, 2014 In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses.
Yasuhiro Takahashi +3 more
doaj +1 more source
Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights
Advanced Intelligent Systems, EarlyView.This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song +8 more
wiley +1 more source
Impact of body biasing on the retention time of gain-cell memories
The Journal of Engineering, 2013 Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM).
Pascal Meinerzhagen +3 more
doaj +1 more source
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
, 2017 Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of ...
Benini, Luca +11 more
core +1 more source
Advanced Intelligent Systems, EarlyView.This article introduces an input sparsity‐aware computing‐in‐memory macro featuring novel bidirectional conversion‐skippable analog‐to‐digital converters. By dynamically adjusting resolution based on element‐level sparsity, the architecture skips redundant most significant bit and least significant bit conversions.
Choongseok Song +2 more
wiley +1 more source