Results 31 to 40 of about 10,751 (237)
Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research
Journal of Sensor and Actuator Networks, 2013 Over the past decade, wireless sensor network research primarily relied on highly-integrated commercial off-the-shelf radio chips. The rigid silicon implementation of the radio stack restricted access to the lower layers; thus, research focused mainly on
Ákos Lédeczi +3 more
doaj +1 more source
DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC [PDF]
Journal of Engineering Science and Technology, 2014 Static Random Access Memory (SRAM) has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST) logic is proposed.
A. KISHORE KUMAR +3 more
doaj
ACE16K: A 128×128 focal plane analog processor with digital I/O [PDF]
, 2002 This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The chip has been designed to achieve
Domínguez Castro, Rafael +3 more
core +1 more source
FPGA-based fault injection design for 16K-point FFT processor
The Journal of Engineering, 2019 There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao +4 more
doaj +1 more source
A Soft Error Self-Resilience Radiation-Hardened 14T SRAM for Aerospace Applications
IEEE AccessVarious charged particles in space threaten memory circuit integrity and dependability, including photons, alpha particles, and high-energy ions outside the Low Earth Orbit region.
Guguloth Anjaneyulu +7 more
doaj +1 more source
Spikes Monitors for FPGAs, an Experimental Comparative Study [PDF]
, 2013 In this paper we present and analyze two VHDL components for monitoring internal activity of spikes fired by silicon neurons inside FPGAs. These spikes monitors encode each spike according to the Address-Event Representation, sending them through a ...
Cerezuela Escudero, Elena +5 more
core +1 more source
, 2019 Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip
Bol, David +2 more
core +1 more source
A programmable microsystem using system-on-chip for real-time biotelemetry [PDF]
, 2005 A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument ...
Cooper, J.M. +6 more
core +1 more source
ACE 16k based stand-alone system for real-time pre-processing tasks [PDF]
, 2005 This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA.
Carranza González, Luis +5 more
core +1 more source
Advanced Materials, EarlyView.We demonstrate a neuromorphic synapse in 2D Fe3GaTe2 flakes. The device operates via a current‐driven transformation from a skyrmion‐lattice to a stripe‐domain state, yielding a linear anomalous Hall resistance response with a tunable slope to enable multiply‐accumulate operations. Simulations confirm its viability in artificial neural networks.
Jixiang Huang +20 more
wiley +1 more source