Results 31 to 40 of about 546 (170)

Wafer Burn-in Method for SRAM in Multi Chip Package [PDF]

Journal of the Korean Institute of Electrical and Electronic Material Engineers, 2005
This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality ...
Jee-Young Yoon, Jang-Woo Ryu, Hoo-Sung Kim, Man-Young Sung   +3 more
openaire   +1 more source

Wafer‐Scale 3D Integration for High‐Density Multi‐Valued Neuromorphic Logic

Advanced Science, EarlyView.
Wafer‐scale 3D vertically integrated multi‐valued logic (MVL) circuits are realized by monolithically integrating a Te/IGZO heterojunction FET with an engineered Te pull‐up FET. Heterointerface‐mediated transport and optimized current matching enable stable ternary operation, while vertical stacking reduces circuit footprint and interconnect complexity,
Chang‐Hyeon Kim, Min Seok Kim, Joong Bum Rhim, Tae In Kim, Hyuck‐In Kwon, Ick‐Joon Park   +5 more
wiley   +1 more source

Single ended 12T cntfet sram cell with high stability for low power smart device applications

e-Prime: Advances in Electrical Engineering, Electronics and Energy
Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at ...
S. Jayanthi, P. Raja, M. Elangovan, T.S. Murugesh   +3 more
doaj   +1 more source

Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks

Advanced Electronic Materials, EarlyView.
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley   +1 more source

Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference

Advanced Electronic Materials, EarlyView.
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho, Dae‐won Kim, Yujin Kim, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi   +6 more
wiley   +1 more source

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

Low-power adiabatic 9T static random access memory

The Journal of Engineering, 2014
In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses.
Yasuhiro Takahashi, Nazrul Anuar Nayan, Toshikazu Sekine, Michio Yokoyama   +3 more
doaj   +1 more source

Highly‐Uniform Passive Crossbar Arrays of Resistive Switching Random Access Memory (RRAM) for In‐Memory Computing Applications

Advanced Electronic Materials, EarlyView.
Passive resistive memory arrays promise efficient in‐memory computing but suffer from sneak paths and programming variability. Here, highly uniform 32 × 32 passive RRAM crossbars are programmed with multilevel precision below 3% error and 99.5% yield.
S. Ricci, P. Mannocci, M. Porzani, D. Bridarolli, F. Carletti, M. Farronato, D. Ielmini   +6 more
wiley   +1 more source

Impact of body biasing on the retention time of gain-cell memories

The Journal of Engineering, 2013
Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM).
Pascal Meinerzhagen, Adam Teman, Alexander Fish, Andreas Burg   +3 more
doaj   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source