Results 11 to 20 of about 546 (170)
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography [PDF]
Journal of Hardware and Systems Security, 2019 AbstractIn today’s globalized integrated circuit (IC) ecosystem, untrusted foundries are often procured to build critical systems since they offer state-of-the-art silicon with the best performance available. On the other hand, ICs that originate from trusted fabrication cannot match the same performance level since trusted fabrication is often ...
Ioannis Karageorgos +3 more
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Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
IET Computers & Digital Techniques, 2021 The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law.
Marshal Raj +2 more
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Micromachines, 2022 Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories.
Mohammed Altaf Ahmed, Suleman Alnatheer
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Algorithm for matching physical and logical addressing in memory chips using laser sources
Безопасность информационных технологий, 2020 The paper presents the developed algorithm for correlating the physical and logical addressing in memory chips using laser radiation sources to determine the nature of failures in radiation tests.
Viacheslav A. Chepov +2 more
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Design of 10T SRAM cell with improved read performance and expanded write margin
IET Circuits, Devices and Systems, 2021 The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes.
Ashish Sachdeva, V. K. Tomar
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Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
IET Computers & Digital Techniques, 2021 Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs.
T. Nirmalraj +2 more
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Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research
Journal of Sensor and Actuator Networks, 2013 Over the past decade, wireless sensor network research primarily relied on highly-integrated commercial off-the-shelf radio chips. The rigid silicon implementation of the radio stack restricted access to the lower layers; thus, research focused mainly on
Ákos Lédeczi +3 more
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DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC [PDF]
Journal of Engineering Science and Technology, 2014 Static Random Access Memory (SRAM) has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST) logic is proposed.
A. KISHORE KUMAR +3 more
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FPGA-based fault injection design for 16K-point FFT processor
The Journal of Engineering, 2019 There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao +4 more
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A Soft Error Self-Resilience Radiation-Hardened 14T SRAM for Aerospace Applications
IEEE AccessVarious charged particles in space threaten memory circuit integrity and dependability, including photons, alpha particles, and high-energy ions outside the Low Earth Orbit region.
Guguloth Anjaneyulu +7 more
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