Results 11 to 20 of about 855 (207)
DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC [PDF]
Journal of Engineering Science and Technology, 2014 Static Random Access Memory (SRAM) has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST) logic is proposed.
A. KISHORE KUMAR +3 more
doaj +1 more source
Atmospheric neutron inducing single event effects on AI chips manufacturing with 8 nm FinFET
Nuclear Engineering and Technology--With the rapid advancement of artificial intelligence (AI) chips in diverse applications, single event effects (SEE) caused by high energy particles in ambient environment have emerged as a critical concern.
Yonghong Li +7 more
doaj +2 more sources
EMERGING ARCHITECTURES FOR PROCESSOR-IN-MEMORY CHIPS: TAXONOMY AND IMPLEMENTATION
RUDN Journal of Engineering Research, 2016 The emergence of PIM (processing-in-memory) die and Date-Centric systems (DCS) and near- data processing approach (NDP) has given rise to the need of developing architectural taxonomy for multi-core PNM (processing near memory) hardware with multi-level ...
A Lapshinsky Valery
doaj +2 more sources
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography [PDF]
Journal of Hardware and Systems Security, 2019 AbstractIn today’s globalized integrated circuit (IC) ecosystem, untrusted foundries are often procured to build critical systems since they offer state-of-the-art silicon with the best performance available. On the other hand, ICs that originate from trusted fabrication cannot match the same performance level since trusted fabrication is often ...
Ioannis Karageorgos +3 more
openaire +1 more source
LOW POWER HIGH THROUGHPUT AND POWER EFFICIENT SRAM DESIGN FOR BIO MEDICAL APPLICATIONS
, 2023 Analysing the voltage supply,rise time, falltime, and delay of the SRAM cells utilising thegpdk 180technology is the aim of this study.The huge growth ofportable battery-operated gadgets in recent years hasmade low power IC design ever more ...
Brinda T (15459224)
core +1 more source
Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
IET Computers & Digital Techniques, 2021 The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law.
Marshal Raj +2 more
doaj +1 more source
An On-line BIST RAM Architecture with Self Repair Capabilities [PDF]
, 2002 The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed.
Di Natale, Giorgio +3 more
core +1 more source
Micromachines, 2022 Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories.
Mohammed Altaf Ahmed, Suleman Alnatheer
doaj +1 more source
Algorithm for matching physical and logical addressing in memory chips using laser sources
Безопасность информационных технологий, 2020 The paper presents the developed algorithm for correlating the physical and logical addressing in memory chips using laser radiation sources to determine the nature of failures in radiation tests.
Viacheslav A. Chepov +2 more
doaj +1 more source
Design of 10T SRAM cell with improved read performance and expanded write margin
IET Circuits, Devices and Systems, 2021 The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes.
Ashish Sachdeva, V. K. Tomar
doaj +1 more source