Results 21 to 30 of about 855 (207)
Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
IET Computers & Digital Techniques, 2021 Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs.
T. Nirmalraj +2 more
doaj +1 more source
Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research
Journal of Sensor and Actuator Networks, 2013 Over the past decade, wireless sensor network research primarily relied on highly-integrated commercial off-the-shelf radio chips. The rigid silicon implementation of the radio stack restricted access to the lower layers; thus, research focused mainly on
Ákos Lédeczi +3 more
doaj +1 more source
Aging-Induced Long-Term Data Remanence in SRAM Cells [PDF]
, 2023 Within the electronics industry, data recovery has been a primary focus of security experts and researches for decades. The vast majority of this research has been performed and realized in the form of hard disk recovery, covering various types of non ...
Hovanes, Joshua
core
Reducing Power Dissipation in SRAM during Test
, 2006 In this paper we analyze the power consumption of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test because of the predictable addressing sequence.
Girard, Patrick +4 more
core +1 more source
FPGA-based fault injection design for 16K-point FFT processor
The Journal of Engineering, 2019 There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao +4 more
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Wafer Burn-in Method of SRAM for Multi Chip Package [PDF]
Transactions on Electrical and Electronic Materials, 2004 This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality
Hoo-Sung Kim +2 more
openaire +1 more source
Minimizing Test Power in SRAM through Reduction of Pre-charge Activity
, 2006 In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power
Girard, Patrick +11 more
core +1 more source
AN EFFICIENT BACK GATE BIASING SRAM ARRAY WITH ROW AND COLUMN BASED SELECTION
, 2022 One of the most indispensible parts of many modern VLSI (Very Large Scale Integration)designs is Static Random Access Memory (SRAM), due to its low consumption of power, higher speed and itdominates the silicon area in various applications.
SHAIK NANNU SAHEB, Dr .RAMESH MARPU, Dr.PRABODH KHAMPARIYA
core +1 more source
A Soft Error Self-Resilience Radiation-Hardened 14T SRAM for Aerospace Applications
IEEE AccessVarious charged particles in space threaten memory circuit integrity and dependability, including photons, alpha particles, and high-energy ions outside the Low Earth Orbit region.
Guguloth Anjaneyulu +7 more
doaj +1 more source
Wafer Burn-in Method for SRAM in Multi Chip Package [PDF]
Journal of the Korean Institute of Electrical and Electronic Material Engineers, 2005 This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality ...
Jee-Young Yoon +3 more
openaire +1 more source