A PUF-and biometric-based lightweight hardware solution to increase security at sensor nodes [PDF]
Security is essential in sensor nodes which acquire and transmit sensitive data. However, the constraints of processing, memory and power consumption are very high in these nodes. Cryptographic algorithms based on symmetric key are very suitable for them.
Arcenegui, Javier +3 more
core +1 more source
Transpose-free variable-size FFT accelerator based on-chip SRAM
Lei Guo +4 more
openalex +3 more sources
Reliable SRAM using NAND‐NOR Gate in beyond‐CMOS QCA technology
The rise in complementary metal‐oxide semiconductor (CMOS) limitations has urged the industry to shift its focus towards beyond‐CMOS technologies to stay in race with Moore’s law.
Marshal Raj +2 more
doaj +1 more source
Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories.
Mohammed Altaf Ahmed, Suleman Alnatheer
doaj +1 more source
Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine [PDF]
Deep neural networks have achieved impressive results in computer vision and machine learning. Unfortunately, state-of-the-art networks are extremely compute and memory intensive which makes them unsuitable for mW-devices such as IoT end-nodes ...
Andri, Renzo +3 more
core +2 more sources
Algorithm for matching physical and logical addressing in memory chips using laser sources
The paper presents the developed algorithm for correlating the physical and logical addressing in memory chips using laser radiation sources to determine the nature of failures in radiation tests.
Viacheslav A. Chepov +2 more
doaj +1 more source
Facility for fast neutron irradiation tests of electronics at the ISIS spallation neutron source [PDF]
The VESUVIO beam line at the ISIS spallation neutron source was set up for neutron irradiation tests in the neutron energy range above 10 MeV. The neutron flux and energy spectrum were shown, in benchmark activation measurements, to provide a neutron ...
A. Paccagnella +10 more
core +2 more sources
Design of 10T SRAM cell with improved read performance and expanded write margin
The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes.
Ashish Sachdeva, V. K. Tomar
doaj +1 more source
PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations [PDF]
We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and "traditional" GRAPE systems is that the former uses FPGA (Field Programmable Gate Array ...
Fukushige, Toshiyuki +3 more
core +4 more sources
Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs.
T. Nirmalraj +2 more
doaj +1 more source

