Results 41 to 50 of about 855 (207)

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

Single ended 12T cntfet sram cell with high stability for low power smart device applications

e-Prime: Advances in Electrical Engineering, Electronics and Energy
Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at ...
S. Jayanthi, P. Raja, M. Elangovan, T.S. Murugesh   +3 more
doaj   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

, 2018
Noise margin analysis of SRAM cell is became more crucial for on chip applications. Currently the technology is migrating towards less than 10nm node and hence it is necessary to measure the noise margin of SRAM cell very effectively, since memory is one
O.P. Singh, G.R. Mishra, P.R. Vaya, Sunil Kumar Ojha   +3 more
core   +1 more source

Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights

Advanced Intelligent Systems, EarlyView.
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song, Changhyeon Han, Joonhyeok Choi, Jongwoo Lee, Hyun‐min Kim, Wongi Hong, Ujin Kim, Sung‐Tae Lee, Daewoong Kwon   +8 more
wiley   +1 more source

Managing Leakage Power and Reliability in Hot Chips Using System Floorplanning and SRAM Design [PDF]

, 2020
Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we ...
Nikil Dutt, Fadi Kurdahi, Magdy Abadir, Aseem Gupta, Kamal Khouri, Amin Djahromi, Ahmed Eltawil   +6 more
core  

A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution

Advanced Intelligent Systems, EarlyView.
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song, Fuxi Cai, Sangsu Park, Zhaoyan Li, Seonghun Lee, Mingyi Rao, Woohyung Choi, Seungin Shin, Yan Zhu, Sujin Chae, Myoungsub Kim, Mingche Wu, Hyejung Choi, Yuan Dao, Jaeyun Yi, Youngman Cho, Seon Yong Cha, Ning Ge, Qiangfei Xia, Soo Gil Kim, Miao Hu, J. Joshua Yang   +21 more
wiley   +1 more source

Low-power adiabatic 9T static random access memory

The Journal of Engineering, 2014
In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses.
Yasuhiro Takahashi, Nazrul Anuar Nayan, Toshikazu Sekine, Michio Yokoyama   +3 more
doaj   +1 more source

Input Sparsity‐Aware Computing‐In‐Memory with Bidirectional Conversion‐Skippable Analog‐to‐Digital Converter

Advanced Intelligent Systems, EarlyView.
This article introduces an input sparsity‐aware computing‐in‐memory macro featuring novel bidirectional conversion‐skippable analog‐to‐digital converters. By dynamically adjusting resolution based on element‐level sparsity, the architecture skips redundant most significant bit and least significant bit conversions.
Choongseok Song, Yonguk Sim, Doo Seok Jeong   +2 more
wiley   +1 more source

Impact of body biasing on the retention time of gain-cell memories

The Journal of Engineering, 2013
Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM).
Pascal Meinerzhagen, Adam Teman, Alexander Fish, Andreas Burg   +3 more
doaj   +1 more source