Results 41 to 50 of about 546 (170)
With the shrinking feature sizes of static random access memory-based field programmable gate arrays (FPGAs), the occurrence probability of multiple-cell upsets (MCUs) in FPGAs continues to increase. This reduces the reliability of FPGAs.
Yue Li +3 more
doaj +1 more source
A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song +21 more
wiley +1 more source
Device and circuit performance analysis of double gate junctionless transistors at L(g) = 18 nm
The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-
Chitrakant Sahu, Jawar Singh
doaj +1 more source
This study introduces a subthreshold in‐memory anomaly detection architecture for wearable ECG monitoring using floating‐gate IGZO content‐addressable memories on a flexible substrate. Area‐engineered coupling provides a high subthreshold slope, while subthreshold operation realizes intrinsic exponential distance evaluation and linear voltage sensing ...
Hyung‐Jun Noh +4 more
wiley +1 more source
A Scalable and Resource‐Efficient Pipelined p‐Computer for Probabilistic Ising Machines
(a) Block diagram of the portfolio optimization problem: given M assets, the goal is to determine the optimal weights w that maximize the expected return (based on the mean historical assets return u), while minimizing the risk, quantified by the assets covariance matrix S.
Deborah Volpe +9 more
wiley +1 more source
An LFSR-based address generator using optimized address partition for low power memory BIST
Power consumption in test mode is much higher than that in normal mode, which is prone to causing circuit damage and reducing the yield of chips. To reduce the power dissipation efficiently, a modified linear feedback shift register(LFSR) is designed to ...
YU Zhi-guo +3 more
doaj
Neuromorphic hardware enables the integration of sensing, memory, and computing for intelligent artificial perception. Recent advances in multimodal fusion further highlight its potential for embodied intelligence and next‐generation human–machine interfaces.
Yixin Zhu +3 more
wiley +1 more source
ABSTRACT Marine operations traditionally rely on human intervention, a costly and disruptive method. Autonomous surface vehicles (ASVs) offer a powerful alternative, capable of operating autonomously, for extended periods, and with various sensors for various missions.
Ayman El Qemmah +4 more
wiley +1 more source
Bio‐inspired computing offers a route to highly energy‐efficient artificial intelligence. The unique physical properties of two‐dimensional (2D) materials can further enhance such computing approaches. This perspective highlights recent developments in 2D materials‐based neuromorphic devices and discusses future opportunities for integrating such novel
Jin Feng Leong +9 more
wiley +1 more source
TrojanWhisper: Evaluating Pre-Trained LLMs to Detect and Localize Hardware Trojans
Existing Hardware Trojan (HT) detection methods face critical limitations: logic testing struggles with scalability, side-channel analysis requires golden reference chips, and formal verification suffers from state-space explosion.
Md Omar Faruque +3 more
doaj +1 more source

