68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI. [PDF]
Guo L +15 more
europepmc +1 more source
SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators. [PDF]
Wang H +8 more
europepmc +1 more source
Low-Power Branch CNN Hardware Accelerator with Early Exit for UAV Disaster Detection Using 16 nm CMOS Technology. [PDF]
Liang YP, Chao WC, Chung CC.
europepmc +1 more source
A Survey of Emerging Memory in a Microcontroller Unit. [PDF]
Qi L, Fan J, Cai H, Fang Z.
europepmc +1 more source
Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution. [PDF]
Chen Z +5 more
europepmc +1 more source
What is next for LLMs? Pushing the boundaries of next-gen AI computing hardware with photonic chips. [PDF]
Li R +9 more
europepmc +1 more source
Wafer-scale fabrication of memristive passive crossbar circuits for brain-scale neuromorphic computing. [PDF]
Choi S +4 more
europepmc +1 more source
Advanced Design for High-Performance and AI Chips. [PDF]
Cao Y, Chen Y, Fan X, Fu H, Xu B.
europepmc +1 more source
Smart Sensor-Based Monitoring Technology for Machinery Fault Detection. [PDF]
Zhang M, Xing X, Wang W.
europepmc +1 more source
A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM. [PDF]
Jiang X +8 more
europepmc +1 more source

