Results 161 to 170 of about 10,430 (199)

SRAM test using on-chip dynamic power supply current sensor

Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236), 2002
We present an overview of power supply current testing of SRAMs and propose a test method to improve the CMOS SRAM test efficiency by using on-chip dynamic power supply current sensors. It is shown that the test method provides full observability of cell switching and allows for a significant reduction in test time.
null Jian Liu, R.Z. Makki
openaire   +1 more source

Accelerating volume rendering using an on-chip SRAM occupancy map

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2002
One of the most severe problems for ray casting architectures is the waste of computation cycles and I/O bandwidth, due to redundant sampling of empty space. While several techniques exist for software implementations to skip these empty regions, few are suitable for hardware implementation. The few which have been presented either require a tremendous
M. Meissner, M. Doggett, U. Kamus, J. Hirche   +3 more
openaire   +1 more source

SPIC - SRAM PUF Intergrated Chip Based Software Licensing Model

2019
A software license key or a product key is a software based key that is used during the installation of a software. This key authorizes a genuine purchase of the software product by the user and verifies the authenticity of the software installation copy.
Vyshak Suresh, R. Manimegalai
openaire   +1 more source

Precharged sram cell for ultra low-power on-chip cache

2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics, 2005
This paper proposes an ultra low-power technique to reduce dynamic and leakage power in SRAM. At write mode, the technique reduces the voltage swing required on the bit lines and depends on the cell itself to amplify the small swing to full swing. HSPICE simulation shows 94.2% write power saving in 0.18nm technology.
R.E. Aly, M.A. Bayoumi
openaire   +1 more source

Mega bit BiCMOS SRAM chip package modelling and performance analysis

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test, 2002
In this paper, a closed-form expression for CMOS SRAM chip propagation delay is developed. This allows accurate calculation of the signal propagation delay of multilayer interconnects within the CMOS SRAM chip and also takes into account the delay of the CMOS SRAM cells driving the branched transmission line and the driving SRAM cell loading aspects of
V.N. Rayapati, B. Kaminska
openaire   +1 more source

An On-Chip Sensor to Monitor NBTI Effects in SRAMs

Journal of Electronic Testing, 2014
The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime.
A. Ceratti, T. Copetti, L. Bolzani, F. Vargas, R. Fagundes   +4 more
openaire   +1 more source

RadHard 16Mbit SRAM Packaged in a Cantilever Die Multi-Chip Module

2007 IEEE Aerospace Conference, 2007
Aeroflex Colorado Springs has developed a 16 Mbit multi-chip module (MCM) SRAM operating on a single 5 V power supply. Using a cantilever die stacking approach, two die are stacked on the top side of the package and two die are stacked on the bottom side of the package for a minimum foot print configuration.
Craig Hafer, Jonathan Mabra, Duane Slocum, Sean Thorne   +3 more
openaire   +1 more source

Providing Root of Trust for ARM TrustZone using On-Chip SRAM

Proceedings of the 4th International Workshop on Trustworthy Embedded Devices, 2014
We present the design, implementation and evaluation of the root of trust for the Trusted Execution Environment (TEE) provided by ARM TrustZone based on the on-chip SRAM Physical Unclonable Functions (PUFs). We first implement a building block which provides the foundations for the root of trust: secure key storage and truly random source. The building
Shijun Zhao, Qianying Zhang, Guangyao Hu, Yu Qin, Dengguo Feng   +4 more
openaire   +1 more source

Automatic gate CD control for a full-chip-scale SRAM device

SPIE Proceedings, 1997
As the minimum feature size in VLSI circuits is reduced less than the wavelength of the exposure light, resolution enhancement technologies (RETs) have been developed. Optical proximity correction (OPC), which is one of RETs, can correct the difference in line width between isolate lines and lines in a dense array.
Chul-Hong Park, Tae K. Kim, Hoong-Joo Lee, Jeong-Taek Kong, Sang-Hoon Lee   +4 more
openaire   +1 more source

Exploring hybrid SRAM/MRAM L2 NUCA stacked on 3D chip-multiprocessors

2014 International SoC Design Conference (ISOCC), 2014
Non-volatile magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with conventional SRAM. The use of hybrid memories (e.g., SRAM and MRAM together) can take advantage of the best characteristics that each technology offers.
null Seunghan Lee, null Kyungsu Kang, null Jongpil Jung, null Chong-Min Kyung   +3 more
openaire   +1 more source