Results 71 to 80 of about 2,464,424 (247)
Modeling and Analysis of Noise Margin in SET Logic
In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model.
Mahapatra, Santanu, Sathe, Chaitanya
core
Edible electronics needs integrated logic circuits for computation and control. This work presents a potentially edible printed chitosan‐gated transistor with a design optimized for integration in circuits. Its implementation in integrated logic gates and circuits operating at low voltage (0.7 V) is demonstrated, as well as the compatibility with an ...
Giulia Coco +8 more
wiley +1 more source
A multi-node-upset-resilient 14T SRAM with high read stability for space applications
This paper proposes a voltage-booster read-decoupled radiation-hardened 14T (BDRH14T) SRAM cell. In harsh environments such as space, radiation can flip the stored data in memory cells, resulting in soft errors, including single-event upset (SEU) and ...
Sung-Jun Lim, Sung-Hun Jo
doaj +1 more source
SRAM stability metric under transient noise [PDF]
ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well ...
Figueras Pàmies, Joan +3 more
core
Coordinated Architectural and Chemical Reinforcement in the Crushing Mandible of a Soldier Termite
The crushing mandible of a soldier termite withstands substantial biting loads despite lacking mineral. Its cuticle is partitioned: convex teeth pair hardness and zinc enrichment with aligned chitin fibers for contact durability, while stiffer concave regions between teeth carry bending loads.
Andrew Tran Nguyen +16 more
wiley +1 more source
This paper presents a novel 8-transistor (8T) static random-access memory (SRAM) cell employing a hybrid cross-coupled inverter (HCCI) structure to address critical challenges in power-constrained computing environments.
Amir Mohammad Karimi Forood +4 more
doaj +1 more source
A scalable, solution‐processed WSe2/ZrO2‐x van der Waals heterostructure realizes a light‐induced field‐tunneling synapse (LIFTS) that activates exclusively under bright illumination, emulating the photopic adaptation of the human retina at the device level.
Kijeong Nam +10 more
wiley +1 more source
Transmission error in spur gears: Static and dynamic finite-element modeling and design optimization [PDF]
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University, 07/10/2010.The gear noise problem that widely occurs in power transmission systems is typically characterised by one or more high amplitude acoustic ...
Tharmakulasingam, Raul
core +5 more sources
Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM
This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET
Yutian Zhang +3 more
doaj +1 more source
Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing
A Memristive‐Gated Transistor for Time‐Encoded Analog In‐Memory Computing — By exploiting the RC delay of a self‐rectifying interface‐type memristor, nonlinear I–V distortion is structurally bypassed, enabling 3‐bit nonvolatile memory, spike‐timing‐based analog encoding, and hardware‐calibrated reservoir‐computing validation within a unified device ...
Yun‐Seo Shin +7 more
wiley +1 more source

