Results 61 to 70 of about 2,464,424 (247)
dynoGP: Deep Gaussian Processes for Dynamic System Identification
This work introduces a novel class of deep models for system identification, dynamical deep Gaussian processes, which combine the strengths of data‐driven methods, such as those based on neural network architectures, with the ability to output a probability distribution for uncertainty representation.
Alessio Benavoli +3 more
wiley +1 more source
Design and circuit applications of PTnMOSFET devices from planar to gate-all-around structures
In this work, we propose a punch-through nMOSFET (PTnMOSFET) as a practical alternative to pMOSFETs by adjusting the source/drain doping concentrations. This PTnMOSFET design simplifies device fabrication by eliminating the need for sizing adjustments or
Jyi-Tsong Lin, Yuan-Yu Chuang
doaj +1 more source
ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM
Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations.
Balotia Suresh Kumar, Amit Mahesh Joshi
openaire +1 more source
Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies [PDF]
SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of ...
Teman, Adam, Adam Teman
core +2 more sources
Predicting extreme defects in additive manufacturing remains a key challenge limiting its structural reliability. This study proposes a statistical framework that integrates Extreme Value Theory with advanced process indicators to explore defect–process relationships and improve the estimation of critical defect sizes. The approach provides a basis for
Muhammad Muteeb Butt +8 more
wiley +1 more source
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell
International audienceTechnology scaling has brought forth major issues related to process variation such as circuit stability and reliability degradation, which are especially problematic for the Static Random Access Memories (SRAM).
Saigné, Frédéric +19 more
core +1 more source
Binder‐free laser powder bed fusion of 8YSZ with a femtosecond laser is used to map process windows linking scan strategy, heat accumulation, and grain growth. Time‐resolved thermography and simulations reveal thermal regimes that enable continuous, vitrified, and fine‐grained 8YSZ surface layers without absorptive additives and demonstrate ...
Markus Kühn +5 more
wiley +1 more source
In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D voltage plane for aging simulation of SRAM circuits.
Zhen Chai, Zhenyu Wu
doaj +1 more source
Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies [PDF]
This dissertation explores the characteristics of Monotonic-Static CMOS and its potential applications in leakage reduction in ultra scaled Bulk-Si technology with significant gate leakage currents.
Irez, Kagan
core +1 more source
More than 10 000 metal‐coated silicon MEMS cantilevers are fabricated and characterized to build a large‐scale experimental dataset spanning multiple vibrational modes. Machine learning algorithms are benchmarked to predict resonance frequency and quality factor, with ensemble based models achieving accuracy approaching experimental uncertainty.
Sina Zare Pakzad +8 more
wiley +1 more source

