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An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs. [PDF]
Pal A +6 more
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Cross-modal privacy-preserving synthesis and mixture-of-experts ensemble for robust ASD prediction. [PDF]
Revathy J, M K.
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Roadmap towards personalized approaches and safety considerations in non-ionizing radiation: from dosimetry to therapeutic and diagnostic applications. [PDF]
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ESICM LIVES 2024. Barcelona, Spain. 5–9 October 2024. [PDF]
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Nanoprobing on the SRAM static noise margin (SNM) soft fail analysis
2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2016As the semiconductor technology continues to scale, the stability and performance of embedded SRAM are growing concerns during the design and analysis stages. Maintaining an acceptable Static Noise Margin (SNM) in the embedded SRAM while scaling the minimum feature size and supply voltage of the integrated circuit (IC) becomes increasingly challenging.
C. Q. Chen +7 more
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2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2015
Nanoprobing techniques have become standard analytical way for real-world device analysis in the modern semiconductor FA lab. The four or six probing of Static noise margin (SNM) and Read noise margin (RNM) could be useful for the SRAM FA. It can justify soft fail and marginal fail to single-bit failure.
null LiLung Lai +3 more
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Nanoprobing techniques have become standard analytical way for real-world device analysis in the modern semiconductor FA lab. The four or six probing of Static noise margin (SNM) and Read noise margin (RNM) could be useful for the SRAM FA. It can justify soft fail and marginal fail to single-bit failure.
null LiLung Lai +3 more
openaire +3 more sources
In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published ...
Qing-Tai Zhao +2 more
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Correction of SNM (Static Noise Margin) of SRAM Using BTI (Bias Temperature Instability) Sensor
INROADS- An International Journal of Jaipur National University, 2018The continuous scaling of CMOS (Complementary Metal-Oxide-semiconductor) technology exponentially increases the power density per unit area (means temperature) and other effects such as lifetime reliability. Bias temperature instability (BTI) is the serious effect which originates due to scaling of MOS, the effect of BTI on the design of SRAM (Static ...
Neeraj Kumar +2 more
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The Static Noise Margin (SNM) of Quaternary SRAM using Quantum SWS-FET
International Journal of High Speed Electronics and SystemsStatic random-access memory (SRAM) is an essential component in the architecture of modern microprocessors and VLSI circuits. The problems of high power consumption, large area, circuit complexity, and data stability against noise are among the most important indicators of performance and obstacles to the current use of SRAM.
B. Saman, E. Heller, F. C. Jain
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