Results 201 to 210 of about 22,014 (257)

2D Materials‐Based Static Random‐Access Memory

Advanced Materials, 2022
Abstract2D transition‐metal dichalcogenide semiconductors, such as MoS2 and WSe2, with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)‐based field‐effect transistor (FET) and static random‐access memory (SRAM) cells analyzing the impact of layer thickness reveals that the ...
Chang‐Ju Liu, Yi Wan, Lain‐Jong Li, Chih‐Pin Lin, Tuo‐Hung Hou, Zi‐Yuan Huang, Vita Pi‐Ho Hu   +6 more
openaire   +4 more sources

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory

ACS Nano
Flexible static random access memory (SRAM) plays an important role in flexible electronics and systems. However, achieving SRAM with a small footprint, high flexibility, and high thermal stability has always been a big challenge. In this work, an ultraflexible six-transistor SRAM with high integration density is realized based on a monolithic three ...
Jiaona Zhang, Wanting Wang, Jiahao Zhu, Chunxiu Wang, Tianyu Zhu, Changbin Zhao, Jialiang Wang, Shengdong Zhang, Xinwei Wang, Kuan-Chang Chang, Hong Meng, Mansun Chan, Min Zhang   +12 more
openaire   +5 more sources

High-speed GaAs static random-access memory

IEEE Transactions on Electron Devices, 1982
An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 V. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions ...
G. Bert, J.-P. Morin, G. Nuzillat, C. Arnodo   +3 more
openaire   +1 more source

Nano-optomechanical static random access memory (SRAM)

2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015
This paper reports an on chip nano-optomechanical SRAM, which is integrated with light modulation system on a single silicon chip. In particular, a doubly-clamped silicon beam shows bistability due to the non-linear optical gradient force generated from a ring resonator. The memory states are assigned with two stable deformation positions, which can be
B. Dong, H. Cai, Y. D. Gu, Z. C. Yang, Y. F. Jin, Y. L. Hao, D. L. Kwong, A. Q. Liu   +7 more
openaire   +1 more source

A 128Kb CMOS static random-access memory

IBM Journal of Research and Development, 1991
This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip
J. L. Chu, H. R. Torabi, F. J. Towler
openaire   +1 more source

A static 4096-bit bipolar random-access memory

IEEE Journal of Solid-State Circuits, 1977
A description of a 23600 mil/SUP 2/, 35-ns 4096/spl times/1 bit bipolar RAM is presented. The historical evolution of density and performance of the 1024/spl times/1 forerunner along with advanced production and circuit techniques indicate the availability of an 11000 mil/SUP 2/, 10-ns, 4096/spl times/1 bipolar RAM by 1981.
W.H. Herndon, W. Ho, R. Ramirez
openaire   +1 more source

Low-power fast static random access memory cell

2010 International Conference on Computer Applications and Industrial Electronics, 2010
In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line.
C. M. R. Prabhu, Ajay Kumar Singh
openaire   +1 more source

A 256 bit Nonvolatile Static Random Access Memory with MNOS Memory Transistors

Japanese Journal of Applied Physics, 1975
A p-channel 256 bit nonvolatile static RAM which is essentially free from any limitation to the memory cycles is developed by means of a new concept of a nonvolatile flip-flop. The logical organization is 64 word × 4 bit. The memory can be operated as a static memory with access time of 400 ns and cycle time of 1 µs under a stable power supply, and as ...
S. Saito, N. Endo, Y. Uchida, T. Tanaka, Y. Nishi, K. Tamaru   +5 more
openaire   +1 more source

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Japanese Journal of Applied Physics, 2017
A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array.
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto   +5 more
openaire   +1 more source