Results 281 to 290 of about 295,937 (324)

On design of multiple-valued static random-access-memory

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002
General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are ...
O. Ishizuka, Z. Tang, H. Matsumoto
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Review of Sense Amplifiers for Static Random Access Memory

IETE Technical Review, 2013
Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs).
Jiafeng Zhu, Na Bai, Jianhui Wu
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Multivalued static random access memory using multivalued FET

International Journal of Electronics Letters, 2018
Quaternary logic is very promising logic for multivalued logic implementation. Four state or quaternary static random access memory (SRAM) can be designed using quantum dot gate-quantum dot channel...
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Testing static and dynamic faults in random access memories

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2003
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed,
S. Hamdioui, Z. Al-Ars, Ad.J. van de Goor   +2 more
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Reliability Improvement of Static Random Access Memory Bit-Cells

2019 International Conference on Smart Systems and Inventive Technology (ICSSIT), 2019
The rapid growth in the semiconductor industry has paved the pathway for tremendous advancement in semiconductor memory technology. Internet of Things (IoT), wireless body sensor nodes and other high-end applications need power-efficient and reliable memories.
E.Jebamalar Leavline, A. Sugantha
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Applications in Static Random Access Memory (SRAM)

2016
Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip.
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A high-speed GaAs 1K static random access memory

IEEE Journal of Solid-State Circuits, 1985
A high-performance 1024/spl times/1-bit static random access memory has been designed and fabricated using an epitaxial GaAs direct coupled logic process. Design rules include 4-/spl mu/m interconnect metallization lines and spaces with 2/spl times/4-/spl mu/m/SUP 2/ vias. MESFETS have 1-/spl mu/m gate length and a self-aligned source and drain.
P. O'Conner, P.G. Flahive, B.J. Roman
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Static Random Access Memory Failure Analysis

International Symposium for Testing and Failure Analysis
Abstract Presentation slides for the ISTFA 2025 Tutorial session “Static Random Access Memory Failure Analysis.”
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Static random access memory using high electron mobility transistors

IEEE Electron Device Letters, 1984
A 4-bit fully decoded static random access memory (RAM) has been designed and fabricated using high electron mobility transistors (HEMT's) with a direct-coupled FET logic approach. The circuit incorporates approximately 50 logic gates. A fully operating memory circuit was demonstrated with an access time of 1.1 ns and a minimum WRITE-enable pulse of ...
S.J. Lee, C.P. Lee, D.L. Hou, R.J. Anderson, D.L. Miller   +4 more
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4096 bit and larger bipolar static random access memories

Microelectronics Journal, 1980
A description of a new 4096 bit, 600mw, 25ns, TAA static TTL RAM with a 2.3 mil 2 cell and a 17,200 mil 2 die is presented. The evolution of static bipolar RAMs is discussed along with an analysis of the power allocation of the current 600mW 4096 bit device. The use of PNP memory cell load devices and Darlington word drivers will lower overhead power
William H. Herndon, Wally Ho, Warren Ong
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