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Low-power data encoding/decoding for energy-efficient static random access memory design

IET Circuits Devices Syst., 2019
This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that
G. Pasandi   +5 more
semanticscholar   +1 more source

Static Random Access Memory Technologies

2009
This chapter contains sections titled: Basic SRAM Architecture and Cell Structures SRAM Selection Considerations High Performance SRAMs Advanced SRAM Architectures Low-Voltage SRAMs BiCMOS Technology SRAMs SOI SRAMs Specialty SRAMs This chapter contains sections titled ...
openaire   +1 more source

Parallel testing of multi-port static random access memories

Microelectronics Journal, 2003
Abstract This paper presents a novel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory.
F. Karimi   +4 more
openaire   +1 more source

Design of ternary clocked adiabatic static random access memory

Journal of Semiconductors, 2011
Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the ...
Pengjun Wang, Fengna Mei
openaire   +1 more source

On design of multiple-valued static random-access-memory

Proceedings of the Twentieth International Symposium on Multiple-Valued Logic, 2002
General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are ...
O. Ishizuka, Z. Tang, H. Matsumoto
openaire   +1 more source

Review of Sense Amplifiers for Static Random Access Memory

IETE Technical Review, 2013
Sense amplifier (SA) is being viewed as one of the most critical circuits in the periphery of high-speed, low-power-embedded static random access memory (SRAMs).
Jiafeng Zhu, Na Bai, Jianhui Wu
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Multivalued static random access memory using multivalued FET

International Journal of Electronics Letters, 2018
Quaternary logic is very promising logic for multivalued logic implementation. Four state or quaternary static random access memory (SRAM) can be designed using quantum dot gate-quantum dot channel...
openaire   +1 more source

Testing static and dynamic faults in random access memories

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2003
The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed,
S. Hamdioui   +2 more
openaire   +1 more source

Reliability Improvement of Static Random Access Memory Bit-Cells

2019 International Conference on Smart Systems and Inventive Technology (ICSSIT), 2019
The rapid growth in the semiconductor industry has paved the pathway for tremendous advancement in semiconductor memory technology. Internet of Things (IoT), wireless body sensor nodes and other high-end applications need power-efficient and reliable memories.
E.Jebamalar Leavline, A. Sugantha
openaire   +1 more source

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

AEU - International Journal of Electronics and Communications, 2023
Ashish Sachdeva   +2 more
semanticscholar   +1 more source

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