Results 91 to 100 of about 129,221 (220)
A Cache Energy Optimization Technique for STT-RAM Last Level Cache [PDF]
, 2013 Sparsh Mittal
openalex +1 more source
, 2015 학위논문(석사) - 한국과학기술원 : 전산학부, 2015.8 ,[iv, 30 p. :]무어의 법칙에 따라 지속적으로 집적도가 높아졌지만, 기존 메모리 셀의 특성상 공정의 한계로 더 이상 기존 기술만으로는 집적도를 높이기가 힘들어지고 있는 추세다. 따라서 STT-RAM (Spin-Transfer Torque RAM), PCM (Phase Change Memory), ReRAM (Resistive RAM) 등의 차세대 메모리로 기존 메모리를 대체하고자 ...
Kim, Hyeonggyu, 김형규
core
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays
, 2020 In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM)
Kulkarni, Shruti R. +3 more
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ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors
Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM\u27s write energy and latency overheads.
Gajaria, Dhruv, Adegbija, Tosiron
core +1 more source
Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM
, 2018 Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings ...
Bohua Li, Wujie Wen, Yukui Pei
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Ram Kumar's favourite place in Kinnaur
, 2018 Ram Kumar describes why Rakchham village is his favorite place in Kinnaur ...
Martinez, Philippe Antoine
core
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures
, 2016 As we integrate data-parallel GPUs with general-purpose CPUs on a single chip, the enormous cache traffic generated by GPUs will not only exhaust the limited cache capacity, but also severely interfere with CPU requests.
Jia Zhan +9 more
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State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers [PDF]
, 2017 Yuanhui Ni +4 more
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A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router
, 2022 Jinzhi Lai, Jueping Cai, Jie Chu
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Ram Kumar's hopes for his children
, 2018 Ram Kumar discusses his hopes for his children and the power of education. The recording was made at Chhitkul's Senior Secondary School, located further down the village, on the river bank, towards the path leading to the military ...
Martinez, Philippe Antoine
core