Results 71 to 80 of about 183,725 (182)

Spin Transfer Torque Induced Switching In Magnetic Tunnel Junction For Stt-Ram Application [PDF]

, 2013
University of Minnesota Ph.D. dissertation. December 2013. Major: Electrical Engineering. Advisor: Jianping Wang. 1 computer file (PDF); viii, 133 pages.This thesis describes experimental studies of the spin transfer torque induced switching in ...
Zhao, Hui
core  

Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM

, 2018
Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings ...
Bohua Li, Wujie Wen, Yukui Pei
core   +1 more source

A Statistical STT-RAM Design View and Robust Designs at Scaled Technologies [PDF]

, 2017
Rapidly increased demands for memory in electronic industry and the significant technical scaling challenges of all conventional memory technologies motivated the researches on the next generation memory technology.
Zhang, Yaojun, Chen, Yiran
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Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

, 2016
The breakdown of Dennard scaling prevents us from powering all transistors simultaneously, leaving a large fraction of dark silicon. This crisis has led to innovative work on power-efficient core and memory architecture designs. However, the research for
Ge, Fen, Zhan, Jia, Zhao, Jishen, Xie, Yuan, Ouyang, Jin   +4 more
core   +1 more source

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach

, 2015
Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide range of write speeds from 1 to 100 ns have been reported for STT-RAM.
Zheng, Yang, Niu, Dimin, Xie, Yuan, Kang, Seung H., Zhu, Xiaochun, Xu, Cong   +5 more
core   +1 more source

An Adaptive ECC Scheme for Runtime Write Failure Suppression of STT-RAM Cache [PDF]

, 2016
Spin-transfer torque random access memory (STT-RAM) features many attractive charac- teristics, including near-zero standby power, nanosecond access time, small footprint, etc.
Wang, Xue
core  

A statistical STT-RAM retention model for fast memory subsystem designs

, 2017
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory (NVM) solution to implement on-chip caches and off-chip main memories for its high integration density and short access time, but it suffers from considerable write ...
Liu, Zihao, Wen, Wujie, Wujie Wen, Jin, Yier, Quan, Gang, Gang Quan, Yier Jin, Zihao Liu, Jiang, Lei, Lei Jiang   +9 more
core   +1 more source

OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches

, 2013
Emerging memory technologies are explored as potential alternatives to traditional SRAM/DRAM-based memory architecture in future microprocessor designs.
Xiangyu Dong, Wang, Jue, Dong, Xiangyu, Yuan Xie, Xie, Yuan, Jue Wang   +5 more
core   +1 more source

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing

, 2014
High reliability, availability, and serviceability are critical for modern large-scale computing systems. As an effective error recovery mechanism, checkpointing has been widely used in such systems for their survival from unexpected failures.
Cong Xu, Xiangyu Dong, Tao Zhang, Chi, Ping, Dong, Xiangyu, Yuan Xie, Xie, Yuan, Ping Chi, Xu, Cong, Zhang, Tao   +9 more
core   +1 more source

DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors

, 2019
Spin-transfer torque RAMs (STT-RAMs) have been studied as a promising alternative to SRAMs in emerging caches and main memories due to their low leakage power and high density. However, STT-RAMs, also have drawbacks of high dynamic write energy and long
Gajaria, Dhruv Mayur
core   +2 more sources