Results 81 to 90 of about 129,221 (220)

The measurement of agitation in neurocognitive disorders: A systematic review

open access: yesAlzheimer's &Dementia, Volume 21, Issue S3, December 2025.
Abstract Background Agitation is a common and distressing behavior in persons with neurocognitive disorders. However, efforts to understand and develop interventions for agitation, historically considered only as a symptom, have been complicated by heterogeneity in the definition, identification, and measurement of agitation.
Dylan X. Guan   +24 more
wiley   +1 more source

coqui-ai/STT: Coqui STT 1.4.0-alpha.0

open access: yes, 2022
STT - The deep learning toolkit for Speech-to-Text.
github-actions[bot]
core   +1 more source

Deterministic Writing of Field‐Free and Unipolar Spin‐Transfer Torque Magnetic Random‐Access Memory

open access: yesAdvanced Functional Materials, Volume 35, Issue 37, September 11, 2025.
Deterministic unipolar‐switching STT‐MRAM with field‐free operation is experimentally demonstrated. The device features a compact 4F2 cell architecture using a diode as the access device and a single magnetic tunneling junction. Unlike conventional bipolar switching STT‐MRAM requiring a three‐terminal access transistor in the array, this design offers ...
Ming‐Chun Hong   +22 more
wiley   +1 more source

Carbon Nanotube 3D Integrated Circuits: From Design to Applications

open access: yesAdvanced Functional Materials, Volume 35, Issue 34, August 22, 2025.
As Moore's law approaches its physical limits, carbon nanotube (CNT) 3D integrated circuits (ICs) emerge as a promising alternative due to the miniaturization, high mobility, and low power consumption. CNT 3D ICs in optoelectronics, memory, and monolithic ICs are reviewed while addressing challenges in fabrication, design, and integration.
Han‐Yang Liu   +3 more
wiley   +1 more source

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

open access: yes, 2011
Spin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-volatile memory which can be embedded into standard CMOS process. A wide range of write speeds from 1ns to 100ns have been reported for STT-RAM. The switching current of
Cong Xu   +11 more
core   +1 more source

Adaptive placement and migration policy for an STT-RAM-based hybrid cache

open access: yes, 2014
Emerging Non-Volatile Memories (NVM) such as Spin-Torque Transfer RAM (STT-RAM) and Resistive RAM (RRAM) have been explored as potential alternatives for traditional SRAM-based Last-Level-Caches (LLCs) due to the benefits of higher density and lower ...
Wang, Zhe   +9 more
core   +1 more source

Design of non-destructive single-sawtooth pulse based readout for STT-RAM by NVM-SPICE

open access: yes, 2012
Spin-transfer torque random access memory (STTRAM) is one promising candidate for future non-volatile memory based computing, because of its fast access time, high integration density and non-volatility.
Yang Shang   +5 more
core   +1 more source

Cross-Layer Optimization for Multilevel Cell STT-RAM Caches

open access: yesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Spin-transfer torque random access memory (STT-RAM), as an emerging nonvolatile memory technology, provides very dense array structure and extremely low leakage power consumption. It demonstrates a great potential in replacing conventional static random access memory technology to develop the next-generation on-chip cache memory of microprocessors and ...
Xiuyuan Bi   +3 more
openaire   +1 more source

Mitigating Read Disturbance Errors in STT-RAM Caches by Using Data Compression

open access: yes, 2019
Due to its high density and close to SRAM read latency, spin transfer torque RAM (STT-RAM) is considered one of the most promising emerging memory technologies for designing large last level caches (LLCs).
Mittal, Sparsh
core   +1 more source

STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption [PDF]

open access: yes, 2019
Current applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) it may become prohibitive in ...
Monreal Arnal, Teresa   +4 more
core   +1 more source

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