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Successive-approximation based CMOS process-scalable hybrid ADCs (本文)

Successive-approximation based CMOS process-scalable hybrid ADCs (本文)
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Successive-approximation based CMOS process-scalable hybrid ADCs (要旨)

Successive-approximation based CMOS process-scalable hybrid ADCs (要旨)
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Predictive Successive Approximation ADC

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
As the demand for better performance in terms of speed and power efficiency of the hardware increases because of the blooming industries such as the Internet of Things (IoT), the science and engineering tries to keep up. IoT is especially interested in faster interaction with the physical world at next to no cost, which is where the value of ...
Jovan Mitrovic, Yiqiao Zhang, Zeljko Ignjatovic   +2 more
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Session 21 overview: Successive-approximation ADCs

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010
For many years, successive-approximation ADCs have been the standard architecture for very-low-power and low-speed applications. For moderate-to-high speed applications, other ADC structures such as flash and pipeline have been traditionally the architecture of choice.
Un-Ku Moon, Tatsuji Matsuura
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A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

Journal of Circuits, Systems and Computers, 2011
A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator.
XIAN TANG, KONG PANG PUN
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Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

IEICE Transactions on Electronics, 2009
Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area.
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda   +11 more
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A Successive Approximation ADC Simulation Project

ASME 1992 International Computers in Engineering Conference: Volume 1 — Artificial Intelligence; Expert Systems; CAD/CAM/CAE; Computers in Fluid Mechanics/Thermal Systems, 1992
Abstract This paper describes a three week long project designed for first year graduate students in mechanical engineering taking a course in Modern Instrumentation. The project entails constructing a successive approximation analog-to-digital converter without a controller, developing a control sequence, and implementing it to produce ...
T. Gary Yip, Elizabeth B. Nadworny
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Adaptive successive approximation ADC for biomedical acquisition system

Microelectronics Journal, 2013
This work proposes a low-power adaptive successive approximation ADC that operates in 12-bit and 8-bit resolution for data acquisition in biomedical system. A fully differential architecture and an energy-efficient switching scheme are employed. The modified switching operation allows the output voltage of the DAC capacitor array to approach the common
Hui-Wen Chang, Hong-Yi Huang, Yi-Hsiang Juan, Wei-Song Wang, Ching-Hsing Luo   +4 more
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Compressive sampling with a successive approximation ADC architecture

2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011
This paper proposes a compressive sampling scheme based on random temporal sampling using a successive approximation register (SAR) ADC architecture. Variable wordlength data samples at random sampling times would be produced by the SAR converter, so a modified reconstruction algorithm is proposed to recover signals that are sparse or compressible in a
Chenchi Luo, James H. McClellan
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Jittered random sampling with a successive approximation ADC

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2014
This paper proposes a randomly jittered temporal sampling scheme with a successive approximation register (SAR) ADC. The sampling time points are jittered around a uniform sampling clock. A control logic is implemented on a traditional SAR ADC to force it to terminate the sample conversion before reaching the full precision at the jittered time points.
Chenchi Eric Luo, Lingchen Zhu
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