Results 171 to 180 of about 14,821 (206)

A successive-approximation-register ADC architecture for digital background calibration in high speed ADCs

2014 International Conference on Advanced Technologies for Communications (ATC 2014), 2014
In this paper, a digital background calibration scheme using an 8-b 10-MS/s successive approximation register (SAR) ADC to calibrate an 8-b 100-MS/s pipelined folding ADC is presented. In order to sample high frequency differential input signals, a new SAR ADC architecture based on the monotonic switching procedure is also proposed.
Binh-Son Le, Duc-Hung Le, Trong-Tu Bui
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All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture

IEEE Transactions on Circuits and Systems I: Regular Papers, 2011
The “split ADC” architecture enables fully digital calibration and correction of nonlinearity errors due to capacitor mismatch in a successive approximation (SAR) ADC. The die area of a single ADC design is split into two independent halves, each converting the same input signal.
John A. McNeill, Ka Yan Chan, Michael C. W. Coln, Christopher L. David, Cody Brenneman   +4 more
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Mathematical study of successive approximation ADC's channel width

Nuclear Instruments and Methods, 1970
Abstract The influence of input and weight voltage variations, on channel width is examined. To obtain a mathematical expression for the differential linearity, the channel width is treated as a function of L t n - the channel width defined by the weights only. In a second step, L t n is supposed to be variable.
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An 8-bit 35-MS/s successive approximation register ADC

2015 IEEE International Conference on Progress in Informatics and Computing (PIC), 2015
An 8-bit 35-MS/s successive approximation register analog-to-digital converter implemented in 0.18µm CMOS process is presented in this paper. To reduce the total power consumption, split capacitor DAC structure coupled with Merged Capacitor Switching (MCS) technique is used.
null Xiucheng Zhou, null Ying Zhang, null Yun Su   +2 more
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Low-Power Successive Approximation ADCS for Wireless Applications

2011
This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of ...
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Mismatch aware power and area optimization of successive-approximation ADCs

2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010
In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and
Jia Mao, Fredrik Jonsson, Li-Rong Zheng
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An 8-bit, 1mW successive approximation ADC in SOI CMOS

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003
A low-power 8-bit successive approximation Analog to Digital Converter (ADC) was designed and fabricated in a 0.5/spl mu/m Silicon on Sapphire CMOS technology. The ADC is capable of 32MHz operation, producing 1.23MS/s, consuming 1.5mW at 3.3V supply.
E. Culurciello, A. Andreou
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100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

Journal of Circuits, Systems and Computers, 2014
This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed.
Sarafi, Sahar, Hadidi, Kheyrollah, Abbaspour, Ebrahim, Aain, Abu Khari, Abbaszadeh, Javad   +4 more
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A Low-Power, Small-Size 10-Bit Successive-Approximation ADC

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2005
A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 μm CMOS double-poly double-metal n-well process.
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ADC Using Successive Approximation Method

Journal of Xidian University, 2020
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