Results 11 to 20 of about 14,821 (206)
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology [PDF]
Journal of Electrical and Computer Engineering Innovations, 2017 A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper.
S. Mahdavi
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Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
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A 1.2v ΔΣ ADC Modulator Using 4-bit SAR Quantizer for Biomedical Applications by using 65nm CMOS Technology [PDF]
MATEC Web of ConferencesThis research focuses on enhancing Sigma-Delta ADC modulators for biomedical applications by leveraging the working principle of Successive Approximation ADC circuits.
Lakshmi Bhavani G. +6 more
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Micromachines, 2022 As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field.
Dongdong Chen +6 more
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A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications [PDF]
, 2016 This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain ...
Carrasco Robles, Manuel +4 more
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A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning
IEEE Access, 2019 This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ...
Yusaku Hirai +6 more
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A low-power reconfigurable ADC for biomedical sensor interfaces [PDF]
, 2009 This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm.
Delgado Restituto, Manuel +3 more
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A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s [PDF]
, 2010 This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and
Elzakker, Michiel van +5 more
core +2 more sources
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2023 The analog-to-digital converter (ADC) is not only a key component in analog in-memory computing (IMC) accelerators but also a bottleneck for the efficiency and accuracy of these systems. While the tradeoffs between power consumption, latency, and area in
Matthew Spear +5 more
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Electronics Letters, 2023 This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of ...
Jaehyuk Lee +9 more
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