Results 21 to 30 of about 14,821 (206)
Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC [PDF]
, 2017 This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application.
Cen, Yuanjun +5 more
core +1 more source
Design Techniques for Energy-Efficient Analog-to-Digital Converters
IEEE Open Journal of the Solid-State Circuits Society, 2023 The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period.
Moonhyung Jang +6 more
doaj +1 more source
Recent progress on CMOS successive approximation ADCs [PDF]
IEEJ Transactions on Electrical and Electronic Engineering, 2016 Recent progress in CMOS integrated successive approximation (SAR) analog‐to‐digital converters (ADCs) is remarkable in terms of architecture and performance. Because of the inherent non‐necessity of active circuit elements such as operational amplifiers, the SAR architecture is suitable for fine CMOS processes. By using a time‐interleaved architecture,
openaire +1 more source
Two‐step, piecewise‐linear SAR ADC with programmable transfer function
Electronics Letters, 2019 A 7‐bit successive approximation register (SAR) analogue‐to‐digital converter (ADC) with programmable transfer functions is presented. Building upon prior art, a two‐step successive approximation technique is used to implement a piecewise‐linear ...
S. Sengupta, M.L. Johnston
doaj +1 more source
Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]
, 2018 Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core +1 more source
Journal of Low Power Electronics and Applications, 2018 This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive ...
Seyed Alireza Zahrai, Marvin Onabajo
doaj +1 more source
High Linearity SAR ADC for Smart Sensor Applications [PDF]
, 2018 This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor ...
Cen, Yuanjun +7 more
core +1 more source
Meta‐stability immunity technique for high speed SAR ADCs
Electronics Letters, 2017 An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre ...
L. Qiu, K. Tang, Y.J. Zheng, L. Siek
doaj +1 more source
Electronics Letters, 2023 This letter proposes a reconfigurable bandpass noise‐shaping successive approximation register analog‐to‐digital converter (ADC) with a cascade of integrators with feedforward (CIFF) structure.
Jonghyun Kim, Younggyun Oh, Hyungil Chae
doaj +1 more source
Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update [PDF]
, 2016 This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and ...
Pickering, J.
core +3 more sources