Results 41 to 50 of about 14,821 (206)

A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction

open access: yesSensors, 2022
This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate
Sang-Hun Lee, Won-Young Lee
doaj   +1 more source

Comparator Design in Sensors for Environmental Monitoring [PDF]

open access: yes, 2018
This paper presents circuit design considerations of comparator in analog-to-digital converters (ADC) applied for a portable, low-cost and high performance nano-sensor chip which can be applied to detect the airborne magnetite pollution nano particulate ...
Fan, Hua   +4 more
core   +1 more source

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

open access: yesIET Circuits, Devices and Systems, 2022
Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong   +8 more
doaj   +1 more source

A Soft-Error-Tolerant SAR ADC with Dual-Capacitor Sample-and-Hold Control for Sensor Systems

open access: yesSensors, 2021
For a reliable and stable sensor system, it is essential to precisely measure various sensor signals, such as electromagnetic field, pressure, and temperature.
Duckhoon Ro, Minseong Um, Hyung-Min Lee
doaj   +1 more source

The ArgoNeuT Detector in the NuMI Low-Energy beam line at Fermilab [PDF]

open access: yes, 2012
The ArgoNeuT liquid argon time projection chamber has collected thousands of neutrino and antineutrino events during an extended run period in the NuMI beam-line at Fermilab.
  +54 more
core   +2 more sources

A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC

open access: yes, 2017
The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented.
Andeen, Timothy   +7 more
core   +1 more source

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

open access: yesIEEE Access, 2020
This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles ...
Reza Inanlou   +2 more
doaj   +1 more source

A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration

open access: yesIEEE Access, 2021
This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to ...
Jae Sik Yoon   +3 more
doaj   +1 more source

Compressed Distributed Gradient Descent: Communication-Efficient Consensus over Networks [PDF]

open access: yes, 2019
Network consensus optimization has received increasing attention in recent years and has found important applications in many scientific and engineering fields.
Bentley, Elizabeth   +4 more
core   +4 more sources

A Time-Domain Comparator for Micro-Powered Successive Approximation ADC [PDF]

open access: yesThe Journal of the Korean Institute of Information and Communication Engineering, 2012
In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector.
Ji-Hun Eo, Sang-Hun Kim, Young-Chan Jang
openaire   +1 more source

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