Results 61 to 70 of about 14,821 (206)

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

Energies, 2018
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be ...
Behnam Samadpoor Rikan, Sang-Yun Kim, Hamed Abbasizadeh, Arash Hejazi, Reza E. Rad, Khuram Shehzad, Keum Cheol Hwang, Youngoo Yang, Minjae Lee, Kang-Yoon Lee   +9 more
doaj   +1 more source

Design of pixel-level ADCs for energy-sensitive hybrid pixel detectors [PDF]

, 2000
Single-photon counting hybrid pixel detectors have shown\ud to be a valid alternative to other types of X-ray imaging\ud devices due to their high sensitivity, low noise, linear behavior\ud and wide dynamic range.
Nauta, Bram, San Segundo Bello, David, Visschers, Jan   +2 more
core   +2 more sources

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

IEEE Access
A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC.
Hamid Karrari, Pietro Andreani, Siyu Tan
doaj   +1 more source

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

Chips
The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs.
Zhaoyang Shen, Shiheng Yang, Jiaxin Liu
doaj   +1 more source

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

IEEE Access, 2019
This paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC).
Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong   +2 more
doaj   +1 more source

A neural network based background calibration for pipelined‐SAR ADCs at low hardware cost

Electronics Letters, 2023
This paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network.
Yuguo Xiang, Min Chen, Danfeng Zhai, Yutong Zhao, Junyan Ren, Fan Ye   +5 more
doaj   +1 more source

Високопродуктивні АЦП із ваговою надлишковістю зі змінними тривалостями тактів порозрядного кодування [PDF]

, 2012
У монографії розглянуто питання побудови високопродуктивних АЦП із ваговою надлишковістю та змінними тривалостями тактів порозрядного наближення.
Azarov, O. D., Harnaha, V. A., Reshetnik, O. O., Азаров, А. Д., Азаров, О. Д., Гарнага, В. А., Гарнага, В. А., Решетник, А. А., Решетнік, О. О.   +8 more
core  

Multipair Massive MIMO Relaying Systems with One-Bit ADCs and DACs

, 2017
This paper considers a multipair amplify-and-forward massive MIMO relaying system with one-bit ADCs and one-bit DACs at the relay. The channel state information is estimated via pilot training, and then utilized by the relay to perform simple maximum ...
Kong, Chuili, Mezghani, Amine, Swindlehurst, A. Lee, Zhang, Zhaoyang, Zhong, Caijun   +4 more
core   +1 more source

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

Sensors, 2018
This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique,
Yongkui Yang, Jun Zhou, Xin Liu, Wang Ling Goh   +3 more
doaj   +1 more source

Successive approximation pipelined ADC with one clock cycle conversion rate

Electronics Letters, 2012
An N -bit successive approximation pipelined (SAP) analogue-to-digital converter (ADC) with a conversion rate equal to the clock frequency is presented. The ADC implements the successive approximation algorithm using parallelism and pipelining to sample the input and generate an N -bit digital output at each clock cycle.
S. Ren, J. Emmert
openaire   +1 more source