Results 191 to 200 of about 672 (251)

Governing Without Enforcing: Foundational Legal Infrastructure and the Capacity–Justiciability Gap in AI Rights Protection

Regulation &Governance, EarlyView.
ABSTRACT Across 124 jurisdictions, formal legal architecture for AI‐related rights protection—including data protection legislation, independent oversight authorities, and sanctioning powers—is substantially more developed than the institutional conditions that make those rights operationally enforceable in practice.
Carlos García‐Llorente, Ignacio Olmeda   +1 more
wiley   +1 more source

Access to Safety Net Programs in the U.S. During the COVID‐19 Pandemic: Barriers and Lessons From a Scoping Review

Social Policy &Administration, EarlyView.
ABSTRACT The COVID‐19 pandemic triggered historic expansions of the U.S. social safety net to mitigate unprecedented economic hardship. However, increased government spending and program expansions on paper do not automatically translate into equitable access in practice.
Soohyun Yoon, Jeehae Kang
wiley   +1 more source

Age effect on inter-pulse interval selection for ECAP measurement. [PDF]

Front Neurosci
Wu H, Yang XY, Liang CQ, Yang JM.
europepmc   +1 more source

Incidental Detection of Respiratory Viruses in Lung Transplant Donor‐Recipient Pairs: Exploratory Associations With Clinical Outcomes in a Post Hoc Analysis

Transplant Infectious Disease, EarlyView.
In 53 lung transplant donor‐recipient pairs, community‐acquired respiratory viruses were incidentally detected by syndromic PCR in 13.2% of donor and 20.8% of recipient bronchoalveolar lavages, with exploratory, unadjusted signals towards longer hospitalization and chronic lung allograft dysfunction.
Andrea Lombardi, Letizia Corinna Morlacchi, Giulia Renisi, Lorenzo Rosso, Jacopo Fumagalli, Patrizia Bono, Ilaria Righi, Valeria Rossetti, Arianna Liparoti, Cecilia Azzarà, Davide Mangioni, Laura Alagna, Anna Celotti, Claudia Alteri, Chiara Abbruzzese, Annapaola Callegaro, Francesco Blasi, Giacomo Grasselli, Mario Nosotti, Alessandra Bandera   +19 more
wiley   +1 more source

A near-threshold memristive computing-in-memory engine for edge intelligence. [PDF]

Nat Commun
Wang L, Li W, Zhou Z, An J, Ye W, Li Z, Gao H, Hu H, Liu J, Chen X, Li L, Liu Q, Seok M, Dou C, Liu M.   +14 more
europepmc   +1 more source

A fully-integrated wearable ultrasonic device for continuous blood pressure monitoring

Beker L, Peker S, Altuntop YA, Neşer G, Toymus A, Yılgör E, Yılgör İ, Bardakçı E.   +7 more
europepmc   +1 more source

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An 8-bit 1MHz Successive Approximation Register (SAR) A/D with 7.98 ENOB

2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, 2011
An 8-bit 1MHz Successive Approximation Register (SAR) A/D has been developed. It employs two sampling bootstrapped switches, a charge redistribution DAC, a dynamic comparator and a digital control block. The presented ADC is fabricated in a 0.5µm CMOS process and the active core area is 0.5*1.0 mm2. Measurement results show the A/D achieves 49.8dB peak
null Yafei Ye, null Liyuan Liu, null Fule Li, null Dongmei Li, null Zhihua Wang   +4 more
exaly   +2 more sources

A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)

2018 New Generation of CAS (NGCAS), 2018
This paper presents a bit cycling method to improve the max root mean square (rms) value of differential nonlinearity (DNL) and the max rms value of integral nonlinearity (INL) for successive approximation register (SAR) analog-to-digital converter (ADC). Neither an additional DAC nor any complex correction algorithm are needed in this work, it is only
Hua Fan, Kelin Zhang, Hadi Heidari
exaly   +2 more sources

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015
Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs
Chris Kim
exaly   +2 more sources

A Low Power Dynamic Comparator For A 12-Bit Pipelined Successive Approximation Register (SAR) ADC

2018 4th International Conference on Devices, Circuits and Systems (ICDCS), 2018
210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of various components that can reduce the precision and the power consumption of the device. It has been identified that the main component that causes a high power consumption in the circuit design is the dynamic comparator. The proposed design of the dynamic comparator
D. S. Shylu, S. Jasmine, D. Jackuline Moni   +2 more
exaly   +2 more sources