Results 201 to 210 of about 672 (251)
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0.18um low voltage 12-bit successive-approximation-register analog-to-digital converter (SAR ADC)
2011 3rd Asia Symposium on Quality Electronic Design (ASQED), 2011This paper presents a 0.18um process Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) design that can operate at a low voltage of minimum 1.4V across process corners and temperature with the power consumption of less than 100uW. The design comprises three main blocks namely a fully differential latched comparator, binary-weighted
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The Development of Successive Approximation Register for SAR ADC
2024 Conference of Young Researchers in Electrical and Electronic Engineering (ElCon)Kristina D. Pepelyaeva +1 more
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2017 International Conference on Circuits, System and Simulation (ICCSS), 2017
A new SAR ADC design is presented in this paper, which applies a flash ADC for the segmentation of its dynamic range. An n bit flash component of the proposed ADC divides the dynamic range into 2n segments. Each of these segments are further resolved by finer SAR ADCs.
Sounak Roy +3 more
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A new SAR ADC design is presented in this paper, which applies a flash ADC for the segmentation of its dynamic range. An n bit flash component of the proposed ADC divides the dynamic range into 2n segments. Each of these segments are further resolved by finer SAR ADCs.
Sounak Roy +3 more
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2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE)
Tejas M P, null Venkateshappa
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Tejas M P, null Venkateshappa
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Journal of Nanoelectronics and Optoelectronics, 2020
This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%.
Sheng-Biao An +4 more
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This paper presents a charge redistributed successive approximation register analog-to-digital converter (SAR ADC). Compared with the traditional Digital-Analog Convertor (DAC), the power consumption of the DAC scheme is reduced by 90%, the area is reduced by 60%.
Sheng-Biao An +4 more
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2017 IEEE 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI), 2017
A novel and reliable high-resolution and high-speed SAR ADC is presented in this paper. In the proposed article, a new compound R-2R/C structure is utilized in order to achieve both high-resolution and high-speed SAR ADC simultaneously. As simulation results verify that, at 1.8 V and 100 MS/s sampling rate with a Nyquist input, the ADC achieves an SNDR
Sina Mahdavi, Esmail Ghadimi
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A novel and reliable high-resolution and high-speed SAR ADC is presented in this paper. In the proposed article, a new compound R-2R/C structure is utilized in order to achieve both high-resolution and high-speed SAR ADC simultaneously. As simulation results verify that, at 1.8 V and 100 MS/s sampling rate with a Nyquist input, the ADC achieves an SNDR
Sina Mahdavi, Esmail Ghadimi
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International Journal of Electrical Engineering and Computer Science
Signals are converted, processed and transmitted digitally exploiting the limitations of the sensory organs of humans, approximating their speech, image and videos but the real world is analog. Interfacing analog and digital systems is necessary to fully leverage the power of digital computation.
Aditya Pradeep Atre +2 more
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Signals are converted, processed and transmitted digitally exploiting the limitations of the sensory organs of humans, approximating their speech, image and videos but the real world is analog. Interfacing analog and digital systems is necessary to fully leverage the power of digital computation.
Aditya Pradeep Atre +2 more
openaire +1 more source
NOISE-SHAPING SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER
2022TRIPATHI PRATEEK +3 more
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